HR job title
- Associate Dean - Faculty
- Contact Info
- 1 979 845 5820
- Websites
- ORCiD
- 0000-0002-4839-3830
Walker, Duncan Professor
Positions
- Professor and Graduate Advisor, Computer Science and Engineering, College of Engineering
- Overview
- Publications
- Research
- Teaching
- Works By Students
- Background
- Contact
- Other
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Overview
Publications
selected publications
-
academic article
-
Chakraborty, A., & Walker, D.
(2023).
Topological Heuristics for Scan Test Overhead Reduction. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
42(6), 2043-2054.
-
Zhang, T., Gao, Y., & Walker, D.
(2015).
Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. Journal of Electronic Testing.
31(1), 99-106.
-
Gao, Y., Zhang, T., Pokharel, P., Chakraborty, S., & Walker, D.
(2015).
Pseudo Functional Path Delay Test through Embedded Memories. Journal of Electronic Testing.
31(1), 35-42.
-
Gulati, K., Jayakumar, N., Khatri, S. P., & Walker, D.
(2008).
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration.
41(3), 399-412.
-
Wang, J., Walker, D., Lu, X., Majhi, A., Kruseman, B., Gronthoud, G., ... Eichenberger, S.
(2007).
Modeling power supply noise in delay testing. IEEE Design and Test of Computers.
24(3), 226-234.
-
Walker, D.
(2007).
The coming storm. IEEE Spectrum.
44(5), 6-6.
-
Sabade, S. S., & Walker, D.
(2006).
Estimation of fault-free leakage current using wafer-level spatial information. 14(1), 91-94.
-
Lu, X., Li, Z., Qiu, W. Q., Walker, D., & Shi, W. P.
(2005).
Longest-path selection for delay test under process variation. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
24(12), 1924-1929.
-
Sabade, S. S., & Walker, D. M.
(2005).
IC outlier identification using multiple test metrics. IEEE Design and Test of Computers.
22(6), 586-595.
-
Sabade, S. S., & Walker, D.
(2004).
I-DDQ data analysis using neighbor current ratios. Journal of Systems Architecture.
50(5), 287-294.
-
Sabade, S. S., & Walker, D. M.
(2004).
I-DDX-based test methods: A survey. ACM Transactions on Design Automation of Electronic Systems.
9(2), 159-198.
-
Li, Z., Lu, X., Qiu, W. Q., Shi, W. P., & Walker, D.
(2003).
A circuit level fault model for resistive bridges. ACM Transactions on Design Automation of Electronic Systems.
8(4), 546-559.
-
Walker, D. M.
(2002).
Concerns about engineers [5]. Electronic Design -New York then Hasbrouck Heights then Cleveland Oh-.
50(26), 26.
-
Sabade, S. S., & Walker, D.
(2002).
I-DDQ test: Will it survive the DSM challenge?. IEEE Design and Test of Computers.
19(5), 8-16.
-
Stanojevic, Z., Balachandran, H., Walker, D., Lakhani, F., Jandhyala, S., Saxena, J., & Butler, K. M.
(2000).
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. International Test Conference.
729-738.
-
Lee, C. Y., & Walker, D.
(2000).
PROBE: a PPSFP simulator for resistive bridging faults. 105-110.
-
Choi, B., & Walker, D.
(2000).
Timing analysis of combinational circuits including capacitive coupling and statistical process variation. 49-54.
-
Zhao, L., Walker, D., & Lombardi, F.
(1999).
I
DDQ testing of input/output resources of SRAM-based FPGAs. Proceedings of the Asian Test Symposium. 375-380.
-
Walker, D. M.
(1999).
Cable modem at home - The author responds. IEEE Spectrum.
36(6), 6-+.
-
Lee, J., Walker, D., Milor, L., Peng, Y., & Hill, G.
(1999).
IC performance prediction for test cost reduction. IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings.
111-114.
-
Nayak, D., & Walker, D.
(1999).
Simulation-based design error diagnosis and correction in combinational digital circuits. 70-78.
-
Zhao, L., Walker, D., & Lombardi, F.
(1998).
I-DDQ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays. IEEE Transactions on Computers.
47(10), 1136-1152.
-
Balasubramaniam, S., Sarwar, A. K., & Walker, D.
(1997).
Yield learning in integrated circuit package assembly. IEEE Transactions on Components, Packaging and Manufacturing Technology. Part C. Manufacturing.
20(2), 133-141.
-
GAITONDE, D. D., & WALKER, D.
(1995).
HIERARCHICAL MAPPING OF SPOT DEFECTS TO CATASTROPHIC FAULTS - DESIGN AND APPLICATIONS. IEEE Transactions on Semiconductor Manufacturing.
8(2), 167-177.
-
Griep, S., Khare, B., Lemme, R., Papenberg, U., SchmittLandsiedel, D., Maly, W., ... Zettler, T.
(1994).
Application of defect simulation as a tool for more efficient failure analysis. Quality and Reliability Engineering International.
10(4), 297-302.
-
GILES, M. D., BONING, D. S., CHIN, G. R., DIETRICH, W. C., KARASICK, M. S., LAW, M. E., ... WONG, A. S.
(1994).
SEMICONDUCTOR WAFER REPRESENTATION FOR TCAD. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
13(1), 82-95.
-
WALKER, D., KELLEN, C. S., SVODOBA, D. M., & STROJWAS, A. J.
(1993).
THE CDB HCDB SEMICONDUCTOR WAFER REPRESENTATION SERVER. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
12(2), 283-295.
-
WALKER, D., & NYDICK, D. S.
(1990).
DVLASIC - CATASTROPHIC FAULT YIELD SIMULATION IN A DISTRIBUTED-PROCESSING ENVIRONMENT. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
9(6), 655-664.
-
Chakraborty, A., & Walker, D.
(2023).
Topological Heuristics for Scan Test Overhead Reduction. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
42(6), 2043-2054.
-
book
-
Walker, D.
(1987).
Yield Simulation for Integrated Circuits. Springer Nature.
-
Walker, D.
(1987).
Yield Simulation for Integrated Circuits. Springer Nature.
-
chapter
-
Krishnendu, C.
(2017).
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. Sandeep, K. G. (Eds.),
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits.
(pp. 23-48).
CRC Press.
-
Walker, D., & Hsiao, M. S.
(2008).
DELAY TESTING. SYSTEM-ON-CHIP TEST ARCHITECTURES: NANOMETER DESIGN FOR TESTABILITY.
(pp. 263-306).
Elsevier.
-
Walker, D. M., & Hsiao, M. S.
(2008).
Chapter 6 Delay Testing. System-on-Chip Test Architectures.
(pp. 263-306).
Elsevier.
-
Huang, J., Li, J., & (Hank) Walker, D. M.
(2006).
Logic and Fault Simulation. VLSI Test Principles and Architectures.
(pp. 105-159).
Elsevier.
-
Huang, J., Li, J., & Walker, D. M.
(2006).
Chapter 3 Logic and Fault Simulation. VLSI Test Principles and Architectures.
(pp. 105-159).
Elsevier.
-
Sakallah, K. A., Walker, D. M., & Nassif, S. R.
(2003).
Timing, Test and Manufacturing Overview. The Best of ICCAD.
(pp. 551-562).
Springer Nature.
-
Walker, D., Kibarian, J. K., Kellen, C. S., & Strojwas, A. J.
(1993).
A TCAD Framework for Development and Manufacturing. Technology CAD Systems.
(pp. 83-111).
Springer Nature.
-
Krishnendu, C.
(2017).
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits. Sandeep, K. G. (Eds.),
Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits.
(pp. 23-48).
CRC Press.
-
conference paper
-
Chakraborty, A., & Walker, D.
(2020).
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
1-4.
-
Biswas, P., & Walker, D.
(2017).
Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. 141-146.
-
Zhang, T., & Walker, D.
(2015).
Impact of Test Compression on Power Supply Noise Control. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
161-166.
-
Chakraborty, A., & Walker, D.
(2015).
Optimizing VMIN of ROM Arrays Without Loss of Noise Margin. 397-402.
-
Chakraborty, S., & Walker, D.
(2015).
At-Speed Path Delay Test. 39-42.
-
Gao, Y., Zhang, T., Chakraborty, S., & Walker, D.
(2014).
Delay Test of Embedded Memories. 65-68.
-
Zhang, T., Gao, Y., & Walker, D.
(2014).
Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise. 61-64.
-
Zhang, T., & Walker, D.
(2014).
Improved Power Supply Noise Control for Pseudo Functional Test. 1-6.
-
Bian, K., Walker, D., & Khatri, S. P.
(2014).
Techniques to Improve the Efficiency of SAT based Path Delay Test Generation. Proceedings of the IEEE International Conference on VLSI Design.
50-55.
-
Bian, K., Walker, D., Khatri, S. P., & Lahiri, S.
(2013).
Mixed Structural-Functional Path Delay Test Generation and Compaction. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
7-12.
-
Zhang, T., & Walker, D.
(2013).
Power Supply Noise Control in Pseudo Functional Test. 1-6.
-
Gope, D., & Walker, D.
(2012).
Maximizing Crosstalk-Induced Slowdown during Path Delay Test. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
159-166.
-
Jiang, Z., Wang, Z., Wang, J., & Walker, D.
(2011).
Levelized Low Cost Delay Test Compaction Considering IR-Drop Induced Power Supply Noise. 52-57.
-
Walker, D.
(2009).
Challenges in Delay Testing of Integrated Circuits. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
81-82.
-
Wang, Z., & Walker, D.
(2009).
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric. 59-64.
-
Shah, N., Samanta, R., Zhang, M., Hu, J., & Walker, D.
(2008).
Built-In Proactive Tuning System for Circuit Aging Resilience. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
96-+.
-
Wang, Z., & Walker, D.
(2008).
Dynamic compaction for high quality delay test. 243-248.
-
Walker, D.
(2007).
The essential role of test in DFM. International Test Conference.
1-1.
-
Walker, D.
(2007).
The essential role of test in DFM. International Test Conference.
1035-1035.
-
Kim, H. S., & Walker, D.
(2006).
Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits. Proceedings - International Workshop on Microprocessor Test and Verification.
76-82.
-
Xue, B., & Walker, D.
(2006).
Is I-DDQ test of microprocessors feasible?. Proceedings - International Workshop on Microprocessor Test and Verification.
63-+.
-
Qiu, W., Walker, D., Simpson, N., Reddy, D., & Moore, A.
(2006).
Comparison of Delay Tests on Silicon. International Test Conference.
1-10.
-
Wang, J., Walker, D., Majhi, A., Kruseman, B., Gronthoud, G., Villagra, L. E., van de Wiel, P., & Eichenberger, S.
(2006).
Power supply noise in delay testing. International Test Conference.
510-+.
-
Qiu, W., Walker, D., Simpson, N., Reddy, D., & Moore, A.
(2006).
Comparison of delay tests on silicon. International Test Conference.
347-+.
-
Wang, J., Yue, Z., Lu, X., Qiu, W., Shi, W., & Walker, D.
(2005).
A Vector-Based Approach for Power Supply Noise Analysis in Test Compaction. International Test Conference.
1-10.
-
Lu, X., Li, Z., Qiu, W. Q., Walker, D., & Shi, W. P.
(2005).
A circuit level fault model for resistive shorts of MOS gate oxide. Proceedings - International Workshop on Microprocessor Test and Verification.
97-102.
-
Wu, L., & Walker, D.
(2005).
A fast algorithm for critical path tracing in VLSI digital circuits. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
178-186.
-
Xue, B., & Walker, D.
(2005).
IDDQ Test Using Built-In Current Sensing of Supply Line Voltage Drop. International Test Conference.
1-10.
-
Jung, E., & Walker, D.
(2005).
Reliable Energy Efficient Routing in Wireless Sensor Networks. 1-8.
-
Wang, J., Lu, X., Qiu, W. Q., Yue, Z. D., Fancler, S., Shi, W. P., & Walker, D.
(2005).
Static compaction of delay tests considering power supply noise. 235-240.
-
Xue, B., & Walker, D.
(2005).
Technology Scaling Issues of an IDDQ Built-In Current Sensor. 10-15.
-
Qiu, W. Q., Lu, X., Wang, J., Li, Z., Walker, D., & Shi, W. P.
(2004).
A statistical fault coverage metric for realistic path delay faults. 37-42.
-
Qiu, W., Wang, J., Walker, D., Lu, X., Li, Z., & Shi, W.
(2004).
A Statistical Fault Coverage Metric for Realistic Path Delay Faults. 1-6.
-
Qiu, W. Q., Wang, J., Lu, X., Li, Z., Walker, D., & Shi, W. P.
(2004).
At-speed test for path delay faults using practical techniques. 61-66.
-
Xue, B., & Walker, D.
(2004).
Built-In Current Sensor for IDDQ Test. 3-9.
-
Sabade, S., & Walker, D.
(2004).
Comparison of NCR effectiveness with a reduced I-DDQ vector set. 65-70.
-
Sabade, S. S., & Walker, D.
(2004).
Comparison of effectiveness of current ratio and delta-I-DDQ tests. Proceedings of the IEEE International Conference on VLSI Design.
889-894.
-
Sabade, S. S., & Walker, D.
(2004).
Comparison of wafer-level spatial I-DDQ estimation methods: NNR versus NCR. 17-22.
-
Qiu, W. Q., Wang, J., Walker, D., Reddy, D., Lu, X. A., Li, Z., Shi, W. P., & Balachandran, H.
(2004).
K longest paths per gate (KLPG) test generation for scan-based sequential circuits. International Test Conference.
223-231.
-
Lu, X., Li, Z., Qiu, W. Q., Walker, D., & Shi, W. P.
(2004).
Longest path selection for delay test under process variation. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
98-103.
-
Lu, X., Li, Z., Qiu, W., Walker, D., & Shi, W.
(2004).
PARADE: PARAmetric Delay Evaluation Under Process Variation **This research was supported in part by the SRC grant 000-TJ-844, NSF grants CCR-0098329, CCR-0113668, EIA-0223785, and ATP grant 512-0266-2001. 276-280.
-
Lu, X., Li, Z., Qiu, W. Q., Walker, D., & Shi, W.
(2004).
PARADE: PARAmetric delay evaluation under process variation. 276-280.
-
Qiu, W. Q., & Walker, D.
(2003).
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. International Test Conference.
592-601.
-
Li, Z., Lu, X., Qiu, W. Q., Shi, W. P., & Walker, D.
(2003).
A circuit level fault model for resistive opens and bridges. 379-384.
-
Sabade, S. S., & Walker, D.
(2003).
CROWNE: Current Ratio outliers with neighbor estimator. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
132-139.
-
Sabade, S. S., & Walker, D.
(2003).
CROWNE: Current ratio outliers with neighbor estimator. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
132-139.
-
Prasad, A., & Walker, D.
(2003).
Chip level power supply partitioning for I-DDQ testing using built-in current sensors. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
140-147.
-
Prasad, A., & Walker, D.
(2003).
Chip level power supply partitioning for I
DDQ testing using built-in current sensors. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems. 140-147.
-
Qiu, W., Lu, X., Li, Z., Walker, D., & Shi, W.
(2003).
CodSim - A combined delay fault simulator. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
79-88.
-
Qiu, W. Q., Lu, X., Li, Z., Walker, D., & Shi, W. P.
(2003).
CodSim - A combined delay fault simulator. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
79-86.
-
Sabade, S. S., & Walker, D.
(2003).
Immediate neighbor difference I-DDQ test (INDIT) for outlier identification. Proceedings of the IEEE International Conference on VLSI Design.
361-366.
-
Qiu, W. Q., & Walker, D.
(2003).
Testing the path delay faults of ISCAS85 circuit c6288. Proceedings - International Workshop on Microprocessor Test and Verification.
19-24.
-
Sabade, S. S., & Walker, D.
(2003).
Use of multiple I-DDQ test metrics for Outlier identification. 31-38.
-
Sabade, S. S., & Walker, D. M.
(2002).
Evaluation of effectiveness of median of absolute deviations outlier rejection-based I-DDQ testing for burn-in reduction. 81-86.
-
Sabade, S. S., & Walker, D.
(2002).
NCR: A self-scaling, self-calibrated metric for I-DDQ outlier identification. 392-395.
-
Sabade, S. S., & Walker, D.
(2002).
Neighbor current ratio (NCR): A new metric for I-DDQ data analysis. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
381-389.
-
Kim, H., Walker, D., & Colby, D.
(2001).
A practical built-in current sensor for I-DDQ testing. International Test Conference.
405-414.
-
Cao, W. L., Walker, D., & Mukherjee, R.
(2001).
An efficient solution to the storage correspondence problem for large sequential circuits. 181-186.
-
Stanojevic, Z., & Walker, D.
(2001).
FedEx - A fast bridging fault extractor. International Test Conference.
696-703.
-
Sabade, S., & Walker, D.
(2001).
Improved wafer-level spatial analysis for I-DDQ limit setting. International Test Conference.
82-91.
-
Stanojevic, Z., Balachandran, H., Walker, D., Lakhani, F., & Jandhyala, S.
(2000).
Defect localization using physical design and electrical test information. ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings.
108-115.
-
Walker, D.
(2000).
Requirements for practical I-DDQ testing of deep submicron circuits. 15-20.
-
Sar-Dessai, V. R., & Walker, D.
(1999).
Resistive bridge fault modeling, simulation and test generation. International Test Conference.
596-605.
-
Walker, D.
(1999).
Design for Yield and Reliability is MORE Important Than DFT. International Test Conference.
1146-1146.
-
Sar-Dessai, V., & Walker, D.
(1998).
Accurate fault modeling and fault simulation of resistive bridges. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
102-107.
-
Zhao, L., Walker, D., & Lombardi, F.
(1998).
Bridging fault detection in FPGA interconnects using I
DDQ . 95-104.
-
Zhao, L., Walker, D., & Lombardi, F.
(1998).
Detection of bridging faults in logic resources of configurable FPGAs using I-DDQ. International Test Conference.
1037-1046.
-
Unni, T. A., & Walker, D.
(1998).
Model-based I-DDQ pass/fail limit setting. 43-47.
-
Sarwar, A., Balasubramaniam, S., & Walker, D.
(1996).
Yield learning model for integrated circuit package assembly. 341-346.
-
Liao, Y. Y., & Walker, D.
(1996).
Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages. International Test Conference.
767-775.
-
Gaitonde, D. D., Maly, W., & Walker, D.
(1996).
Fault probability prediction for array based designs. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.
30-38.
-
Balachandran, H., & Walker, D.
(1996).
Improvement of SRAM-based failure analysis using calibrated Iddq testing. 130-136.
-
Liao, Y. Y., & Walker, D.
(1996).
Optimal voltage testing for physically-based faults. 344-353.
-
Luong, G. M., & Walker, D.
(1996).
Test generation for global delay faults. International Test Conference.
433-442.
-
Kwon, Y. J., & Walker, D.
(1995).
Contamination control using production test data. 70-76.
-
Gaitonde, D. D., Walker, D., & Maly, W.
(1995).
Accurate yield estimation of circuits with redundancy. IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems.
155-163.
-
Lakkapragada, S., & Walker, D.
(1995).
Defect-tolerant processor arrays. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon.
228-237.
-
Ramakrishnan, V., & Walker, D.
(1995).
IC performance prediction system. International Test Conference.
336-344.
-
NAIK, R., & WALKER, D.
(1995).
LARGE INTEGRATED CROSSBAR SWITCH. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon.
217-227.
-
Ramakrishnan, V., & Walker, D.
(1995).
Model-based product quantity control. 389-395.
-
Kwon, Y. J., & Walker, D.
(1995).
Yield learning via functional test data. International Test Conference.
626-635.
-
WALKER, D.
(1993).
ARCHITECTURES FOR CATASTROPHIC AND DELAY FAULT-TOLERANCE. 47-56.
-
Gaitonde, D. D., Khare, J., Walker, D., & Maly, W.
(1993).
Estimation of reject ratio in testing of combinatorial circuits. 319-325.
-
Khare, J., Griep, S., Oberle, H., Maly, W., Schmitt-Landsiedel, D., Kollmer, U., & Walker, D.
(1993).
Key attributes of an SRAM testing strategy required for effective process monitoring. 84-89.
-
GAITONDE, D. D., & WALKER, D.
(1993).
TEST QUALITY AND YIELD ANALYSIS USING THE DEFAM DEFECT TO FAULT MAPPER. 202-205.
-
Walker, D.
(1992).
Critical area analysis. 281-290.
-
Walker, D.
(1992).
Tolerance of delay faults. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
207-216.
-
WALKER, D., KELLEN, C. S., & STROJWAS, A. J.
(1991).
A SEMICONDUCTOR WAFER REPRESENTATION DATABASE AND ITS USE IN THE PREDATOR PROCESS EDITOR AND STATISTICAL SIMULATOR. 579-584.
-
Gaitonde, D., & Walker, D.
(1991).
Circuit-level modeling of spot defects. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
63-66.
-
WALKER, D.
(1990).
SOFT-PROGRAMMABLE BYPASS SWITCH DESIGN FOR DEFECT-TOLERANT ARRAYS. 236-242.
-
Walker, D.
(1989).
Yield analysis for fault-tolerant arrays. 257-265.
-
Chakraborty, A., & Walker, D.
(2020).
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
1-4.
-
patent
-
Walker, D., & Kim, H.
(2005).
System and method for detecting quiescent current in an integrated circuit
-
Walker, D., & Kim, H.
(2005).
System and method for detecting quiescent current in an integrated circuit
Research
principal investigator on
investigator on
Teaching
teaching activities
- CSCE491 Hnr-research Instructor
- CSCE606 Software Engineering Instructor
- CSCE680 Test & Diag Digital Syst Instructor
- CSCE684 Professional Internship Instructor
- CSCE685 Directed Studies Instructor
- CSCE691 Research Instructor
- ECEN680 Test&diag Digital Syst Instructor
- ECEN684 Professional Internship Instructor
- ECEN684 Professional Internship: In-ab Instructor
- ECEN685 Directed Studies Instructor
- ECEN691 Research Instructor
- ENGR681 Professional Develpmnt Instructor
Works By Students
chaired theses and dissertations
-
Balasubramanian, Vijay (2007-04). Variance reduction and outlier identification for IDDQ testing of integrated chips using principal component analysis.
-
Bian, Kun (2013-12). Efficient Path Delay Test Generation with Boolean Satisfiability.
-
Biswas, Prasenjit (2016-08). Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra.
-
Boga, Viswanath (2016-05). Optimization of Pseudo Functional Path Delay Test Through Embedded Memories.
-
Chakraborty, Avijit (2015-11). Observability Driven Path Generation for Delay Test.
-
Chakraborty, Swati (2015-04). At-Speed Path Delay Test.
-
Gao, Yukun (2015-04). Pseudo Functional Path Delay Test through Embedded Memories.
-
Gharaibeh, Ammar (2010-01). A Behavioral Model of a Built-in Current Sensor for IDDQ Testing.
-
Gill, Arjun (2013-05). Optimizing Test Pattern Generation Using Top-Off ATPG Methodology for Stuck-AT, Transition and Small Delay Defect Faults.
-
Gope, Dibakar (2012-10). Maximizing Crosstalk-Induced Slowdown During Path Delay Test.
-
Jiang, Zhongwei (2012-02). Low Cost Power and Supply Noise Estimation and Control in Scan Testing of VLSI Circuits.
-
Jung, Eun Jae (2009-05). Creation and maintenance of a communication tree in wireless sensor networks.
-
Kim, Hyun Sung (2009-06). Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.
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Lahiri, Shayak (2012-02). Pseudofunctional Delay Tests For High Quality Small Delay Defect Testing.
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Parikh, Shaishav Shailesh (2005-08). Testing tri-state and pass transistor circuit structures.
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Pokharel, Punj (2013-07). Path Delay Test Through Memory Arrays.
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Prasad, Abhijit (2003-12). Power supply partitioning for placement of built-in current sensors for IDDQ testing.
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Qiu, Wangqi (2007-04). Fault simulation and test generation for small delay faults.
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Sabade, Sagar Suresh (2005-05). Integrated circuit outlier identification by multiple parameter correlation.
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Shrija, . (2016-12). A Reconfigurable Approximate JPEG Encoder Implemented On FPGA Platform.
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Tamilarasan, Karthik Prabhu (2012-02). Built-In Self Test (BIST) for Realistic Delay Defects.
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Veluswami, Senthilkumar (2005-11). Statistical static timing analysis considering process variations and crosstalk.
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Wang, Jing (2009-05). Power supply noise in delay testing.
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Wang, Zheng (2011-08). High Quality Compact Delay Test Generation.
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Wu, Lei (2009-05). An efficient logic fault diagnosis framework based on effect-cause approach.
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Xue, Bin (2006-04). Voltage sensing based built-in current sensor for IDDQ test.
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Yang, Xu (2009-05). On the development of Voice over IP.
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Zhang, Tengteng (2015-12). High Quality Test Generation Targeting Power Supply Noise.
Background
education and training
- Ph.D. in Computer Science, Carnegie Mellon University - (Pittsburgh, Pennsylvania, United States) 1986
- M.S. in Computer Science, Carnegie Mellon University - (Pittsburgh, Pennsylvania, United States) 1984
- B.S. in Engineering (Honors), California Institute of Technology - (Pasadena, California, United States) 1979
awards and honors
Contact
first name
- Duncan
has last name
- Walker
mailing address
-
Texas A&M University
Computer Science & Engineering
3112 TAMU
College Station, TX 77843-3112
USA
Other
- d-walker@tamu.edu