HR job title
- Associate Dean for Graduate Programs
- Contact Info
- 1 979 845 5820
- Websites
Walker, Duncan Professor - Term Appointment
Positions
- Professor and Graduate Advisor, Computer Science and Engineering, College of Engineering
- Overview
- Publications
- Research
- Teaching
- Works By Students
- Background
- Contact
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Overview
Publications
selected publications
-
academic article
-
Zhang, T., Gao, Y., & Walker, D.
(2015).
Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. Journal of Electronic Testing.
31(1), 99-106.
-
Gao, Y., Zhang, T., Pokharel, P., Chakraborty, S., & Walker, D.
(2014).
Pseudo Functional Path Delay Test through Embedded Memories. Journal of Electronic Testing.
31(1), 35-42.
-
Gulati, K., Jayakumar, N., Khatri, S. P., & Walker, D.
(2008).
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration.
41(3), 399-412.
-
Wang, J., Walker, D. M., Lu, X., Majhi, A., Kruseman, B., Gronthoud, G., ... Eichenberger, S.
(2007).
Modeling Power Supply Noise in Delay Testing. IEEE Design and Test.
24(3), 226-234.
-
Sabade, S. S., & Walker, D.
(2006).
Estimation of Fault-Free Leakage Current Using Wafer-Level Spatial Information. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS.
14(1), 91-94.
-
Lu, X., Li, Z., Qiu, W., Walker, D., & Shi, W.
(2005).
Longest-Path Selection for Delay Test Under Process Variation. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
24(12), 1924-1929.
-
Sabade, S. S., & Walker, D. M.
(2005).
IC outlier identification using multiple test metrics. IEEE Design and Test.
22(6), 586-595.
-
Sabade, S. S., & Walker, D. M.
(2004).
I DDX -based test methods: A survey. ACM Transactions on Design Automation of Electronic Systems.
9(2), 159-198.
-
Sabade, S. S., & Walker, D.
(2004).
IDDQ data analysis using neighbor current ratios. Journal of Systems Architecture.
50(5), 287-294.
-
Li, Z., Lu, X., Qiu, W., Shi, W., & Walker, D.
(2003).
A circuit level fault model for resistive bridges. ACM Transactions on Design Automation of Electronic Systems.
8(4), 546-559.
-
Walker, D. M.
(2002).
Concerns about engineers [5]. Electronic Design.
50(26), 26.
-
Sabade, S. S., & Walker, D.
(2002).
I/sub DDQ/ test: will it survive the DSM challenge?. IEEE Design and Test.
19(5), 8-16.
-
Stanojevic, Z., Balachandran, H., Walker, D., Lakbani, F., Jandhyala, S., Saxena, J., & Butler, K. M.
(2000).
Computer-aided fault to defect mapping (CAFDM) for defect diagnosis. IEEE International Test Conference (TC).
729-738.
-
Lee, C. Y., & Walker, D.
(2000).
PROBE: a PPSFP simulator for resistive bridging faults. 105-110.
-
Choi, B., & Walker, D.
(2000).
Timing analysis of combinational circuits including capacitive coupling and statistical process variation. 49-54.
-
Zhao, L., Walker, D., & Lombardi, F.
(1999).
I
DDQ testing of input/output resources of SRAM-based FPGAs. ATS 2003: 12TH ASIAN TEST SYMPOSIUM, PROCEEDINGS. 375-380.
-
Lee, J., Walker, D., Milor, L., Peng, Y., & Hill, G.
(1999).
IC performance prediction for test cost reduction. ASIC, 2003 Proceedings 5th International Conference on.
111-114.
-
Zhao, L., Walker, D., & Lombardi, F.
(1998).
I/sub DDQ/ testing of bridging faults in logic resources of reconfigurable field programmable gate arrays. IEEE Transactions on Computers.
47(10), 1136-1152.
-
Balasubramaniam, S., Sarwar, A. K., & Walker, D.
(1997).
Yield learning in integrated circuit package assembly. IEEE Transactions on Components Packaging and Manufacturing Technology Part C.
20(2), 133-141.
-
Gaitonde, D. D., & Walker, D.
(1995).
Hierarchical mapping of spot defects to catastrophic faults-design and applications. IEEE Transactions on Semiconductor Manufacturing.
8(2), 167-177.
-
Griep, S., Khare, B., Lemme, R., Papenberg, U., Schmitt‐Landsiedel, D., Maly, W., ... Zettler, T.
(1994).
Application of defect simulation as a tool for more efficient failure analysis. Quality and Reliability Engineering International.
10(4), 297-302.
-
Walker, D., Kellen, C. S., Svoboda, D. M., & Strojwas, A. J.
(1993).
The CDB/HCDB semiconductor wafer representation server. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
12(2), 283-295.
-
Walker, D., & Nydick, D. S.
(1990).
DVLASIC: catastrophic fault yield simulation in a distributed processing environment. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS.
9(6), 655-664.
-
Zhang, T., Gao, Y., & Walker, D.
(2015).
Pattern Generation for Understanding Timing Sensitivity to Power Supply Noise. Journal of Electronic Testing.
31(1), 99-106.
-
chapter
-
Walker, D. M., & Hsiao, M. S.
(2008).
Chapter 6 Delay Testing. System-on-Chip Test Architectures.
(pp. 263-306).
-
Huang, J. L., Li, J., & Walker, D. M.
(2006).
Logic and fault simulation. VLSI Test Principles and Architectures.
(pp. 105-159).
Elsevier.
-
Huang, J., Li, J., & Walker, D. M.
(2006).
Chapter 3 Logic and Fault Simulation. VLSI Test Principles and Architectures.
(pp. 105-159).
-
Sakallah, K. A., Walker, D. M., & Nassif, S. R.
(2003).
Timing, Test and Manufacturing Overview. The Best of ICCAD.
(pp. 551-562).
Springer US.
-
Walker, D. M., & Hsiao, M. S.
(2008).
Chapter 6 Delay Testing. System-on-Chip Test Architectures.
(pp. 263-306).
-
conference paper
-
Chakraborty, A., & Walker, D.
(2020).
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. 1-4.
-
Biswas, P., & Walker, D.
(2017).
Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra. 141-146.
-
Zhang, T., & Walker, D.
(2015).
Impact of Test Compression on Power Supply Noise Control. 161-166.
-
Chakraborty, S., & Walker, D.
(2015).
At-Speed Path Delay Test. 39-42.
-
Chakraborty, A., & Walker, D.
(2015).
Optimizing VMIN of ROM Arrays Without Loss of Noise Margin. 397-402.
-
Gao, Y., Zhang, T., Chakraborty, S., & Walker, D.
(2014).
Delay Test of Embedded Memories. 65-68.
-
Zhang, T., Gao, Y., & Walker, D.
(2014).
Pattern Generation for Post-Silicon Timing Validation Considering Power Supply Noise. 61-64.
-
Zhang, T., & Walker, D. M.
(2014).
Improved Power Supply Noise Control for Pseudo Functional Test. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
1-6.
-
Bian, K., Walker, D., & Khatri, S. P.
(2014).
Techniques to Improve the Efficiency of SAT based Path Delay Test Generation. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
50-55.
-
Bian, K., Walker, D., Khatri, S. P., & Lahiri, S.
(2013).
Mixed Structural-Functional Path Delay Test Generation and Compaction. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
7-12.
-
Zhang, T., & Walker, D. M.
(2013).
Power Supply Noise Control in Pseudo Functional Test. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
1-6.
-
dibakar, G., & Walker, D.
(2012).
Maximizing Crosstalk-Induced Slowdown during Path Delay Test. 2005 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS.
159-166.
-
Jiang, Z., Wang, Z., Wang, J., & Walker, D.
(2011).
Levelized Low Cost Delay Test Compaction Considering IR-Drop Induced Power Supply Noise. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
52-57.
-
Walker, D.
(2009).
Challenges in Delay Testing of Integrated Circuits. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
81-82.
-
Wang, Z., & Walker, D.
(2009).
Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
59-64.
-
Shah, N., Samanta, R., Zhang, M., Hu, J., & Walker, D.
(2008).
Built-In Proactive Tuning System for Circuit Aging Resilience. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
96-104.
-
Wang, Z., & Walker, D.
(2008).
Dynamic Compaction for High Quality Delay Test. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
243-248.
-
Walker, D.
(2007).
The essential role of test in DFM. IEEE International Test Conference (TC).
1-1.
-
Kim, H. S., & Walker, D.
(2006).
Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits. 2013 14th International Workshop on Microprocessor Test and Verification.
76-82.
-
Qiu, W., Walker, D., Simpson, N., Reddy, D., & Moore, A.
(2006).
Comparison of Delay Tests on Silicon. IEEE International Test Conference (TC).
1-10.
-
Wang, J., Walker, D., Majhi, A., Kruseman, B., Gronthoud, G., Villagra, L. E., van de Wiel, P., & Eichenberger, S.
(2006).
Power Supply Noise in Delay Testing. IEEE International Test Conference (TC).
1-10.
-
Xue, B., & Walker, D.
(2005).
Is IDDQ Test of Microprocessors Feasible?. 2013 14th International Workshop on Microprocessor Test and Verification.
63-69.
-
Wu, L., & Walker, D.
(2005).
A Fast Algorithm for Critical Path Tracing in VLSI Digital Circuits. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
178-186.
-
Wang, J., Yue, Z., Lu, X., Qiu, W., Shi, W., & Walker, D.
(2005).
A Vector-Based Approach for Power Supply Noise Analysis in Test Compaction. IEEE International Test Conference (TC).
1-10.
-
Xue, B., & Walker, D.
(2005).
IDDQ Test Using Built-In Current Sensing of Supply Line Voltage Drop. IEEE International Test Conference (TC).
1-10.
-
Jung, E., & Walker, D.
(2005).
Reliable Energy Efficient Routing in Wireless Sensor Networks. 1-8.
-
Wang, J., Lu, X., Qiu, W., Yue, Z., Fancler, S., Shi, W., & Walker, D.
(2005).
Static Compaction of Delay Tests Considering Power Supply Noise. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
235-240.
-
Xue, B., & Walker, D.
(2005).
Technology Scaling Issues of an IDDQ Built-In Current Sensor. 10-15.
-
Qiu, W. Q., Lu, X., Wang, J., Li, Z., Walker, D., Shi, W. P., & society, i. C.
(2004).
A statistical fault coverage metric for realistic path delay faults. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
37-42.
-
Lu, X., Li, Z., Shi, W., Qiu, W., & Walker, D.
(2004).
A Circuit Level Fault Model for Resistive Shorts of MOS Gate Oxide. 2013 14th International Workshop on Microprocessor Test and Verification.
97-102.
-
Qiu, W., Wang, J., Walker, D., Lu, X., Li, Z., & Shi, W.
(2004).
A Statistical Fault Coverage Metric for Realistic Path Delay Faults. 1-6.
-
Qiu, W., Wang, J., Lu, X., Li, Z., Walker, D., & Shi, W.
(2004).
At-Speed Test for Path Delay Faults using Practical Techniques. 61-66.
-
Xue, B., & Walker, D.
(2004).
Built-In Current Sensor for IDDQ Test. 3-9.
-
Sabade, S. S., & Walker, D.
(2004).
Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
889-894.
-
Sabade, S. S., & Walker, D.
(2004).
Comparison of Wafer-Level Spatial IDDQ Estimation Methods: NNR versus NCR. 17-22.
-
Qiu, W., Wang, J., Walker, D., Reddy, D., Lu, X., Li, Z., Shi, W., & Balachandran, H.
(2004).
K Longest Paths Per Gate (KLPG) Test Generation for Scan-Based Sequential Circuits. IEEE International Test Conference (TC).
223-231.
-
Lu, X., Li, Z., Qiu, W., Walker, D., & Shi, W.
(2004).
Longest Path Selection for Delay Test Under Process Variation**This research was supported in part by the SRC grant 000-TJ-844, NSF grants CCR-0098329, CCR-0113668, EIA-0223785, and ATP grant 512-0266-2001. 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC).
98-103.
-
Sabade, S., & Walker, D.
(2004).
On Comparison of NCR Effectiveness with a Reduced IDDQ Vector Set. 1-6.
-
Lu, X., Li, Z., Qiu, W., Walker, D., & Shi, W.
(2004).
PARADE: PARAmetric Delay Evaluation Under Process Variation **This research was supported in part by the SRC grant 000-TJ-844, NSF grants CCR-0098329, CCR-0113668, EIA-0223785, and ATP grant 512-0266-2001. 276-280.
-
Lu, X., Li, Z., Qiu, W. Q., Walker, D., Shi, W., SOCIETY, I. C., SOCIETY, I. C., & SOCIETY, I. C.
(2004).
PARADE: PARAmetric delay evaluation under process variation. 276-280.
-
Qiu, W., & Walker, D.
(2003).
An Efficient Algorithm for Finding the K Longest Testable Paths Through Each Gate in a Combinational Circuit. IEEE International Test Conference (TC).
592-601.
-
Li, Z., Lu, X., Qiu, W., Shi, W., & Walker, D.
(2003).
A Circuit Level Fault Model for Resistive Opens and Bridges. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
379-384.
-
Sabade, S. S., & Walker, D.
(2003).
CROWNE: Current ratio outliers with neighbor estimator. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
132-139.
-
Prasad, A., & Walker, D.
(2003).
Chip Level Power Supply Partitioning for Iddq Testing Using Built-In Current Sensors. 140-147.
-
Prasad, A., & Walker, D.
(2003).
Chip level power supply partitioning for I
DDQ testing using built-in current sensors. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS. 140-147.
-
Qiu, W., Lu, X., Li, Z., Walker, D., & Shi, W.
(2003).
CodSim - A Combined Delay Fault Simulator. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
79-86.
-
Qiu, W., Lu, X., Li, Z., Walker, D., & Shi, W.
(2003).
CodSim - A combined delay fault simulator. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
79-88.
-
Sabade, S. S., & Walker, D.
(2003).
Crowne: Current Ratio Outliers with Neighbor Estimator. 132-139.
-
Sabade, S. S., & Walker, D.
(2003).
Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
361-366.
-
Qiu, W., & Walker, D.
(2003).
Testing the Path Delay Faults of ISCAS85 Circuit c6288. 2013 14th International Workshop on Microprocessor Test and Verification.
19-24.
-
Sabade, S. S., & Walker, D.
(2003).
Use of Multiple IDDQ Test Metrics for Outlier Identification. 31-38.
-
Sabade, S. S., & Walker, D. M.
(2002).
Evaluation of Effectiveness of Median of Absolute Deviations Outlier Rejection-based IDDQ Testing for Burn-in Reduction. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
81-86.
-
Sabade, S. S., & Walker, D.
(2002).
NCR: A Self-scaling, Self-calibrated Metric for IDDQ Outlier Identification. i-392-i-395.
-
Sabade, S. S., & Walker, D.
(2002).
Neighbor Current Ratio (NCR): A New Metric for IDDQ Data Analysis. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
381-389.
-
Kim, H., Walker, D., & Colby, D.
(2001).
A Practical Built-in Current Sensor for IDDQ Testing. IEEE International Test Conference (TC).
405-414.
-
Cao, W., Walker, D., & Mukherjee, R.
(2001).
An efficient solution to the storage correspondence problem for large sequential circuits. 181-186.
-
Stanojevic, Z., & Walker, D.
(2001).
Fedex - a fast bridging fault extractor. IEEE International Test Conference (TC).
696-703.
-
Sabade, S., & Walker, D.
(2001).
Improved Wafer-level Spatial Analysis for IDDQ Limit Setting. IEEE International Test Conference (TC).
82-91.
-
Stanojevic, Z., Balachandran, H., Walker, D., Lakhani, F., & Jandhyala, S.
(2000).
Defect localization using physical design and electrical test information. 10th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop ASMC 99 Proceedings (Cat No99CH36295).
108-115.
-
Walker, D.
(2000).
Requirements for practical I/sub DDQ/ testing of deep submicron circuits. 15-20.
-
Sar-Dessai, V. R., & Walker, D.
(1999).
Resistive bridge fault modeling, simulation and test generation. IEEE International Test Conference (TC).
596-605.
-
Walker, D.
(1999).
Design for Yield and Reliability is MORE Important Than DFT. IEEE International Test Conference (TC).
1146-1146.
-
Zhao, L., Walker, D., & Lombardi, F.
(1998).
Detection of bridging faults in logic resources of configurable FPGAs using I
DDQ . IEEE International Test Conference (TC). 1037-1046.
-
Zhao, L., Walker, D., & Lombardi, F.
(1998).
Bridging fault detection in FPGA interconnects using I
DDQ . 95-104.
-
Liao, Y., & Walker, D.
(1996).
Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages. IEEE International Test Conference (TC).
767-775.
-
Luong, G. M., & Walker, D.
(1996).
Test generation for global delay faults. IEEE International Test Conference (TC).
433-442.
-
Sarwar, A., Balasubramaniam, S., & Walker, D.
(1996).
Yield learning model for integrated circuit package assembly. 341-346.
-
Balachandran, H., & Walker, D.
(1996).
Improvement of SRAM-based failure analysis using calibrated Iddq testing. 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS.
130-136.
-
Liao, Y., & Walker, D.
(1996).
Optimal voltage testing for physically-based faults. 344-353.
-
Kwon, Y. J., & Walker, D.
(1995).
Contamination control using production test data. 70-76.
-
Ramakrishnan, V., & Walker, D.
(1995).
IC performance prediction system. IEEE International Test Conference (TC).
336-344.
-
Ramakrishnan, V., & Walker, D.
(1995).
Model-based product quantity control. 389-395.
-
Kwon, Y. J., & Walker, D.
(1995).
Yield learning via functional test data. IEEE International Test Conference (TC).
626-635.
-
Lakkapragada, S., & Walker, D.
(1995).
Defect-tolerant processor arrays. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon.
228-237.
-
Naik, R., & Walker, D.
(1995).
Large integrated crossbar switch. Proceedings of the Annual IEEE International Conference on Innovative Systems in Silicon.
217-227.
-
Walker, D.
(1993).
Architectures for catastrophic and delay fault tolerance. 47-56.
-
Walker, D.
(1990).
Soft-programmable bypass switch design for defect-tolerant arrays. 236-242.
-
Walker, D.
(1989).
Yield analysis for fault-tolerant arrays. 257-265.
-
Chakraborty, A., & Walker, D.
(2020).
Observability Driven Path Generation for Delay Test Coverage Improvement in Scan Limited Circuits. 1-4.
Research
principal investigator on
investigator on
awards and honors
Teaching
teaching activities
- CSCE491 Hnr-research Instructor
- CSCE606 Software Engineering Instructor
- CSCE680 Test & Diag Digital Syst Instructor
- CSCE684 Professional Internship: In-ab Instructor
- CSCE685 Directed Studies Instructor
- CSCE691 Research Instructor
- ECEN680 Test&diag Digital Syst Instructor
- ECEN684 Professional Internship Instructor
- ECEN684 Professional Internship: In-ab Instructor
- ECEN685 Directed Studies Instructor
- ECEN691 Research Instructor
Works By Students
chaired theses and dissertations
-
Balasubramanian, Vijay (2006-12). Variance reduction and outlier identification for IDDQ testing of integrated chips using principal component analysis.
-
Bian, Kun (2013-12). Efficient Path Delay Test Generation with Boolean Satisfiability.
-
Biswas, Prasenjit (2016-08). Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra.
-
Boga, Viswanath (2016-05). Optimization of Pseudo Functional Path Delay Test Through Embedded Memories.
-
Chakraborty, Avijit (2015-12). Observability Driven Path Generation for Delay Test.
-
Chakraborty, Swati (2015-05). At-Speed Path Delay Test.
-
Gao, Yukun (2015-05). Pseudo Functional Path Delay Test through Embedded Memories.
-
Gharaibeh, Ammar (2009-08). A Behavioral Model of a Built-in Current Sensor for IDDQ Testing.
-
Gill, Arjun (2013-05). Optimizing Test Pattern Generation Using Top-Off ATPG Methodology for Stuck-AT, Transition and Small Delay Defect Faults.
-
Gope, Dibakar (2011-08). Maximizing Crosstalk-Induced Slowdown During Path Delay Test.
-
Jiang, Zhongwei (2010-12). Low Cost Power and Supply Noise Estimation and Control in Scan Testing of VLSI Circuits.
-
Jung, Eun Jae (2007-12). Creation and maintenance of a communication tree in wireless sensor networks.
-
Kim, Hyun Sung (2007-08). Statistical static timing analysis considering the impact of power supply noise in VLSI circuits.
-
Lahiri, Shayak (2011-12). Pseudofunctional Delay Tests For High Quality Small Delay Defect Testing.
-
Parikh, Shaishav Shailesh (2005-08). Testing tri-state and pass transistor circuit structures.
-
Pokharel, Punj (2013-08). Path Delay Test Through Memory Arrays.
-
Prasad, Abhijit (2003-12). Power supply partitioning for placement of built-in current sensors for IDDQ testing.
-
Qiu, Wangqi (2006-12). Fault simulation and test generation for small delay faults.
-
Sabade, Sagar Suresh (2005-05). Integrated circuit outlier identification by multiple parameter correlation.
-
Shrija, . (2016-12). A Reconfigurable Approximate JPEG Encoder Implemented On FPGA Platform.
-
Tamilarasan, Karthik Prabhu (2010-12). Built-In Self Test (BIST) for Realistic Delay Defects.
-
Veluswami, Senthilkumar (2005-08). Statistical static timing analysis considering process variations and crosstalk.
-
Wang, Jing (2007-08). Power supply noise in delay testing.
-
Wang, Zheng (2010-05). High Quality Compact Delay Test Generation.
-
Wu, Lei (2007-12). An efficient logic fault diagnosis framework based on effect-cause approach.
-
Xue, Bin (2005-12). Voltage sensing based built-in current sensor for IDDQ test.
-
Yang, Xu (2008-05). On the development of Voice over IP.
-
Zhang, Tengteng (2015-12). High Quality Test Generation Targeting Power Supply Noise.
Background
education and training
- Ph.D. in Computer Science, Carnegie Mellon University - (Pittsburgh, Pennsylvania, United States) 1986
- M.S. in Computer Science, Carnegie Mellon University - (Pittsburgh, Pennsylvania, United States) 1984
- B.S. in Engineering (Honors), California Institute of Technology - (Pasadena, California, United States) 1979
Contact
first name
- Duncan
has last name
- Walker
mailing address
-
Texas A&M University
Computer Science & Engineering
3112 TAMU
College Station, TX 77843-3112
USA
Other
- d-walker@tamu.edu