Improved Path Recovery in Pseudo Functional Path Delay Test Using Extended Value Algebra
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abstract
2016 IEEE. Scan-based delay test achieves high fault coverage due to its improved controllability and observability. This is particularly important for our K Longest Paths Per Gate (KLPG) test approach, since path delay test has additional necessary assignments, compared to transition fault test. Some percentage of flip-flops is not scan, due to delay, area or power constraints. Their outputs are 'uncontrollable' since they cannot be initialized. These uncontrollable values block path sensitization, resulting in path delay fault coverage loss. In this work, we extend the traditional Boolean algebra to eleven values, including the 'uncontrolled' value as a legal logic state to reduce pessimism in path sensitization analysis. Experiments on ISCAS89 benchmarks with 10% non-scan flip-flops and eleven-value algebra increased tested path-count by 1.9x for robust test, and 2.2x for non-robust test, compared to the traditional algebra. Transition fault coverage increased by 70% and CPU time per path decreased by 40%.
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2017 30th International Conference on VLSI Design and 2017 16th International Conference on Embedded Systems (VLSID)
