HIERARCHICAL MAPPING OF SPOT DEFECTS TO CATASTROPHIC FAULTS - DESIGN AND APPLICATIONS Academic Article

abstract

• This paper describes the DEfect to FAult Mapper (DEFAM), and its use in integrated circuit test quality analysis and yield prediction. DEFAM analyzes the effects of spot defects on a design during the manufacturing process, and computes the probability of circuit faults that may occur. Unlike traditional tools, DEFAM exploits the design hierarchy to reduce the required analysis effort. It also reports faults in terms of the design hierarchy, which is essential for many applications. Yield analysis results are given for CMOS designs of up to 164K transistors. Test quality analysis results are given for an adder module. 1995 IEEE

authors

• Walker, Duncan

published proceedings

• IEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING
• IEEE Transactions on Semiconductor Manufacturing

author list (cited authors)

• GAITONDE, D. D., & WALKER, D.
• Gaitonde, D. D., & Walker, D.

citation count

• 18

complete list of authors

• GAITONDE, DD||WALKER, DMH
• Gaitonde, DD||Walker, DMH

publication date

• May 1995

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Semiconductor Manufacturing  Journal

Digital Object Identifier (DOI)

• 10.1109/66.382278

start page

• 167

end page

• 177

volume

• 8

issue

• 2

URL

• http://dx.doi.org/10.1109/66.382278