DVLASIC - CATASTROPHIC FAULT YIELD SIMULATION IN A DISTRIBUTED-PROCESSING ENVIRONMENT Academic Article

abstract

• Simulation of local process disturbances is a computationally intensive task. The VLASIC (VLSI LAyout Simulation for Integrated Circuits) catastrophic fault yield simulator uses a Monte Carlo method that often requires tens of CPU hours to perform a simulation. In order to reduce the simulation time, we have developed DVLASIC, a distributed version of VLASIC, which is implemented on a network of 25 VAXstation 3200 workstations. DVLASIC achieves a speedup of 13.3 over VLASIC, with an efficiency of 89%. We describe the distributed processing environment and implementation techniques used to obtain this speedup. Large speedups are difficult to obtain on the VLASIC problem due to the expense of Monte Carlo problem generation, and the relatively small problem granularity. The distributed processing environment can be applied to many other CAD problems. 1990 IEEE

authors

• Walker, Duncan

published proceedings

• IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS
• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

author list (cited authors)

• WALKER, D., & NYDICK, D. S.
• Walker, D., & Nydick, D. S.

citation count

• 0

complete list of authors

• WALKER, DMH||NYDICK, DS
• Walker, DMH||Nydick, DS

publication date

• June 1990

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems  Journal

Digital Object Identifier (DOI)

• 10.1109/43.55195

start page

• 655

end page

• 664

volume

• 9

issue

• 6

URL

• http://dx.doi.org/10.1109/43.55195