IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems Journal

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CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network. 40:1640-1647. 2021
Memristor-Based Edge Computing of ShuffleNetV2 for Image Classification. 40:1701-1710. 2021
Hardware Memory Management for Future Mobile Hybrid Memory Systems. 39:3627-3637. 2020
Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices. 39:1498-1510. 2020
Adjusting Learning Rate of Memristor-Based Multilayer Neural Networks via Fuzzy Method. 38:1084-1094. 2019
An Analytical Approach for Error PMF Characterization in Approximate Circuits. 38:70-83. 2019
Capacitance Extraction With Provably Good Absorbing Boundary Conditions. 37:2013-2021. 2018
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing. 37:545-558. 2018
Macro Model of Advanced Devices for Parasitic Extraction. 35:1721-1729. 2016
On Improving the Security of Logic Locking. 35:1411-1424. 2016
Belling the CAD: Toward Security-Centric Electronic System Design. 34:1756-1769. 2015
Guest Editorial: Special Section on Physical Design Techniques for Advanced Technology Nodes. 34:501-501. 2015
LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip. 33:826-838. 2014
Guest editorial: Special section on cross-domain physical optimization. 32:173-174. 2013
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. 31:1558-1571. 2012
$O(mn)$ Time Algorithm for Optimal Buffer Insertion of Nets With $m$ Sinks. 31:437-441. 2012
Guest Editorial Special Section on the 2011 International Symposium on Physical Design. 31:165-166. 2012
Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm. 30:1663-1676. 2011
Simultaneous Technology Mapping and Placement for Delay Minimization. 30:416-426. 2011
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. 29:1342-1353. 2010
Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials. 28:1106-1110. 2009
Gate Sizing for Cell-Library-Based Designs. 28:818-825. 2009
Gate Sizing for Cell-Library-Based Designs. 28:818-825. 2009
Inductance extraction for interconnects in the presence of nonlinear magnetic materials. 28:1106-1110. 2009
Buffering Interconnect for Multicore Processor Designs. 27:2183-2196. 2008
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics. 27:1918-1927. 2008
Robust Clock Tree Routing in the Presence of Process Variations. 27:1385-1397. 2008
Fast Algorithms for Slew-Constrained Minimum Cost Buffering. 26:2009-2022. 2007
Path-Based Buffer Insertion. 26:1346-1355. 2007
Wire Sizing for Non-Tree Topology. 26:872-880. 2007
An Exact Jumper-Insertion Algorithm for Antenna Violation Avoidance/Fixing Considering Routing Obstacles. 26:719-733. 2007
Guest Editorial. 26:617-618. 2007
A Unified Theory of Timing Budget Management. 25:2364-2375. 2006
Fast 3-D Capacitance Extraction by Inexact Factorization and Reduction. 25:2282-2286. 2006
Analytical bound for unwanted clock skew due to wire width variation. 25:1869-1876. 2006
Accurate estimation of global buffer delay within a floorplan. 25:1140-1145. 2006
Reducing clock skew variability via crosslinks. 25:1176-1182. 2006
An O(bn/sup 2/) time algorithm for optimal buffer insertion with b buffer types. 25:484-489. 2006
Longest-path selection for delay test under process variation. 24:1924-1929. 2005
Sparse transformations and preconditioners for 3-D capacitance extraction. 24:1420-1426. 2005
A fast algorithm for optimal buffer insertion. 24:879-891. 2005
A Methodology for the Simultaneous Design of Supply and Signal Networks. 23:1614-1624. 2004
A Divide-and-Conquer Algorithm for 3-D Capacitance Extraction. 23:1157-1163. 2004
SPFD-Based Wire Removal in Standard-Cell and Network-of-PLA Circuits. 23:1020-1030. 2004
Simultaneous Driver Sizing and Buffer Insertion Usinga Delay Penalty Estimation Technique. 23:136-141. 2004
A practical methodology for early buffer and wire resource allocation. 22:573-583. 2003
Buffer insertion with adaptive blockage avoidance. 22:492-498. 2003
A timing-constrained simultaneous global routing algorithm. 21:1025-1036. 2002
A fast hierarchical algorithm for three-dimensional capacitance extraction. 21:330-336. 2002
An efficient and regular routing methodology for datapath designs using net regularity extraction. 21:93-101. 2002
International Symposium on Physical Design (ISPD). 21:c1-c1. 2002
Steiner tree optimization for buffers, blockages, and bays. 20:556-562. 2001
Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model. 19:446-458. 2000
Non-Hanan routing. 18:436-444. 1999
Three-dimensional defect sensitivity modeling for open circuits in ULSI structures. 17:366-371. 1998
A fast algorithm for area minimization of slicing floorplans. 15:1525-1532. 1996
Area minimization for hierarchical floorplans. 436-440. 1994
The CDB/HCDB semiconductor wafer representation server. 12:283-295. 1993
DVLASIC: catastrophic fault yield simulation in a distributed processing environment. 9:655-664. 1990
A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment 2010
Power Grid Analysis and Optimization Using Algebraic Multigrid 2008
Optimal register sharing for high-level synthesis of SSA form programs 2006
Antenna avoidance in layer assignment 2006
Porosity-Aware Buffered Steiner Tree Construction 2004