IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Journal

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STATION: State Encoding-Based Attack-Resilient Sequential Obfuscation. PP:1-1. 2024
Topological Heuristics for Scan Test Overhead Reduction. 42:2043-2054. 2023
DETERRENT: Detecting Trojans Using Reinforcement Learning. PP:1-1. 2023
CKFO: Convolution Kernel First Operated Algorithm With Applications in Memristor-Based Convolutional Neural Network. 40:1640-1647. 2021
Keynote: A Disquisition on Logic Locking. 39:1952-1972. 2020
Thwarting Replication Attack Against Memristor-Based Neuromorphic Computing System. 39:2192-2205. 2020
Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices. 39:1498-1510. 2020
Adjusting Learning Rate of Memristor-Based Multilayer Neural Networks via Fuzzy Method. 38:1084-1094. 2019
An Analytical Approach for Error PMF Characterization in Approximate Circuits. 38:70-83. 2019
Capacitance Extraction With Provably Good Absorbing Boundary Conditions. 37:2013-2021. 2018
SDPR: Improving Latency and Bandwidth in On-Chip Interconnect Through Simultaneous Dual-Path Routing. 37:545-558. 2018
Macro Model of Advanced Devices for Parasitic Extraction. 35:1721-1729. 2016
On Improving the Security of Logic Locking. 35:1411-1424. 2016
Belling the CAD: Toward Security-Centric Electronic System Design. 34:1756-1769. 2015
Special Section on Physical Design Techniques for Advanced Technology Nodes. 34:501-501. 2015
LumiNOC: A Power-Efficient, High-Performance, Photonic Network-on-Chip. 33:826-838. 2014
Special Section on Cross-Domain Physical Optimization. 32:173-174. 2013
O(mn) Time Algorithm for Optimal Buffer Insertion of Nets with m Sinks. 31:437-441. 2012
Special Section on the 2011 International Symposium on Physical Design. 31:165-166. 2012
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. 31:1558-1571. 2012
Simultaneous Technology Mapping and Placement for Delay Minimization. 30:416-426. 2011
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. 29:1342-1353. 2010
Inductance Extraction for Interconnects in the Presence of Nonlinear Magnetic Materials. 28:1106-1110. 2009
Gate Sizing for Cell-Library-Based Designs. 28:818-825. 2009
Gate Sizing for Cell-Library-Based Designs. 28:818-825. 2009
Inductance extraction for interconnects in the presence of nonlinear magnetic materials. 28:1106-1110. 2009
Buffering Interconnect for Multicore Processor Designs. 27:2183-2196. 2008
A Preconditioned Hierarchical Algorithm for Impedance Extraction of Three-Dimensional Structures With Multiple Dielectrics. 27:1918-1927. 2008
Robust clock tree routing in the presence of process variations. 27:1385-1397. 2008
Fast algorithms for slew-constrained minimum cost buffering. 26:2009-2022. 2007
Path-based buffer insertion. 26:1346-1355. 2007
Wire sizing for non-tree topology. 26:872-880. 2007
An exact jumper-insertion algorithm for antenna violation avoidance/fixing considering routing obstacles. 26:719-733. 2007
Special Issue on the 2006 International Symposium on Physical Design. 26:617-618. 2007
A Unified Theory of Timing Budget Management. 25:2364-2375. 2006
Fast 3-D capacitance extraction by inexact factorization and reduction. 25:2282-2286. 2006
Bound for unwanted clock skew due to wire width variation. 25:1869-1876. 2006
Accurate estimation of global buffer delay within a floorplan. 25:1140-1146. 2006
Reducing clock skew variability via crosslinks. 25:1176-1182. 2006
An O(bn(2)) time algorithm for optimal buffer insertion with b buffer types. 25:484-489. 2006
Longest-path selection for delay test under process variation. 24:1924-1929. 2005
Sparse transformations and preconditioners for 3-D capacitance extraction. 24:1420-1426. 2005
A fast algorithm for optimal buffer insertion. 24:879-891. 2005
A Methodology for the Simultaneous Design of Supply and Signal Networks. 23:1614-1624. 2004
A Divide-and-Conquer Algorithm for 3-D Capacitance Extraction. 23:1157-1163. 2004
SPFD-based wire removal in standard-cell and network-of-PLA circuits. 23:1020-1030. 2004
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. 23:136-141. 2004
A practical methodology for early buffer and wire resource allocation. 22:573-583. 2003
Buffer insertion with adaptive blockage avoidance. 22:492-498. 2003
A timing-constrained simultaneous global routing algorithm. 21:1025-1036. 2002
A Fast Hierarchical Algorithm for Three-Dimensional Capacitance Extraction. 21:330-336. 2002
An Efficient and Regular Routing Methodology for Datapath Designs Using Net Regularity Extraction. 21:93-101. 2002
Buffered Steiner Trees for Difficult Instances. 21:3-14. 2002
Steiner Tree Optimization for Buffers, Blockages, and Bays. 20:556-562. 2001
Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model. 19:446-458. 2000
Non-Hanan routing. 18:436-444. 1999
Three-dimensional defect sensitivity modeling for open circuits in ULSI structures. 17:366-371. 1998
A fast algorithm for area minimization of slicing floorplans. 15:1525-1532. 1996
BUILT-IN SELF-TEST FOR C-TESTABLE ILAS. 14:1388-1398. 1995
Area minimization for hierarchical floorplans. 436-440. 1994
SEMICONDUCTOR WAFER REPRESENTATION FOR TCAD. 13:82-95. 1994
THE CDB HCDB SEMICONDUCTOR WAFER REPRESENTATION SERVER. 12:283-295. 1993
DVLASIC - CATASTROPHIC FAULT YIELD SIMULATION IN A DISTRIBUTED-PROCESSING ENVIRONMENT. 9:655-664. 1990
A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment 2010
Power grid analysis and optimization using algebraic multigrid 2008
Optimal Register Sharing for High-Level Synthesis of SSA Form Programs 2006
Antenna avoidance in layer assignment 2006
Porosity-aware buffered steiner tree construction 2004