Steiner tree optimization for buffers, blockages, and bays
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Timing optimization is a critical component of deep submicrometer design and buffer insertion is an essential technique for achieving timing closure. This work studies buffer insertion under the constraint that the buffers either: 1) avoid blockages or 2) are contained within preassigned buffer bay regions. We propose a general Steiner-tree formulation to drive this application and present a maze-routing-based heuristic that either avoids blockages or finds buffer bays. We show that the combination of our Steiner-tree optimization with leading-edge buffer-insertion techniques leads to effective solutions on industry designs.
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
author list (cited authors)
Alpert, C. J., Gandham, G., Jiang Hu, .., Neves, J. I., Quay, S. T., & Sapatnekar, S. S.
complete list of authors
Alpert, CJ||Gandham, G||Neves, JI||Quay, ST||Sapatnekar, SS