HR job title
- Professor
- Contact Info
- 1 979 847 8768
- Websites
Hu, Jiang Professor
Positions
- Professor, Electrical and Computer Engineering, College of Engineering
- Faculty Affiliate, Energy Institute, Texas A&M Engineering Experiment Station (TEES)
Current research: optimization for energy-efficient VLSI circuits, on-chip communication fabrics, dynamic power management, adaptive circuit design, interactions between physical design and system-level design, heuristics for large scale combinatorial optimization.
- Overview
- Publications
- Research
- Teaching
- Works By Students
- Background
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Overview
Publications
selected publications
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academic article
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Zhuo, C., Luo, S., Gan, H., Hu, J., & Shi, Z.
(2020).
Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
39(7), 1498-1510.
-
Sengupta, D., Snigdha, F. S., Hu, J., & Sapatnekar, S. S.
(2019).
An Analytical Approach for Error PMF Characterization in Approximate Circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
38(1), 70-83.
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Lee, S., Shi, C., Wang, J., Sanabria, A., Osman, H., Hu, J., & Sanchez-Sinencio, E.
(2018).
A Built-In Self-Test and
In Situ Analog Circuit Optimization Platform. IEEE Transactions on Circuits and Systems I: Regular Papers. 65(10), 3445-3458.
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Wang, Y., Chen, P. u., Hu, J., Li, G., & Rajendran, J.
(2018).
The Cat and Mouse in Split Manufacturing. IEEE Transactions on Very Large Scale Integration Systems.
26(5), 805-817.
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Won, J., Gratz, P. V., Shakkottai, S., & Hu, J.
(2016).
Resource Sharing Centric Dynamic Voltage and Frequency Scaling for CMP Cores, Uncore, and Memory. ACM Transactions on Design Automation of Electronic Systems.
21(4), 1-25.
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Silva-Martinez, J., Karsilayan, A. I., Hu, J., & Krishnaswamy, H.
(2016).
Special Issue on the 57th International Midwest Symposium on Circuits and Systems. 88(2), 181-183.
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Davoodi, A., Hu, J., Ozdal, M., & Sze, C.
(2015).
Special Section on Physical Design Techniques for Advanced Technology Nodes. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
34(4), 501-501.
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Won, J., Ryu, H., Delbruck, T., Lee, J. H., & Hu, J.
(2015).
Proximity Sensing Based on a Dynamic Vision Sensor for Mobile Devices. IEEE transactions on industrial electronics (1982. Print).
62(1), 536-544.
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Chen, X. i., Hu, J., & Xu, N.
(2014).
Regularity-constrained floorplanning for multi-core processors. Integration.
47(1), 86-95.
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Chen, X. i., Xu, Z., Kim, H., Gratz, P., Hu, J., Kishinevsky, M., & Ogras, U.
(2013).
In-network monitoring and control policy for DVFS of CMP networks-on-chip and last level caches. ACM Transactions on Design Automation of Electronic Systems.
18(4), 1-21.
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Shim, K., & Hu, J.
(2013).
Boostable Repeater Design for Variation Resilience in VLSI Interconnects. IEEE Transactions on Very Large Scale Integration Systems.
21(9), 1619-1631.
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Shim, K., Hu, J., & Silva-Martinez, J.
(2013).
Dual-Level Adaptive Supply Voltage System for Variation Resilience. 21(6), 1041-1052.
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Hu, J., & Koh, C.
(2013).
Special Section on Cross-Domain Physical Optimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
32(2), 173-174.
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Dougherty, E. R., Yoon, B., Qian, X., & Pal, R.
(2012).
Special Issue on Genomic Signal Processing FOREWORD. 20(4), VII-VIII.
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Hu, J., & Koh, C.
(2012).
Special Section on the 2011 International Symposium on Physical Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
31(2), 165-166.
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Ozdal, M. M., Burns, S., & Hu, J.
(2012).
Algorithms for Gate Sizing and Device Parameter Selection for High-Performance Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
31(10), 1558-1571.
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Liu, Y., & Hu, J.
(2011).
GPU-Based Parallelization for Fast Circuit Optimization. ACM Transactions on Design Automation of Electronic Systems.
16(3), 24-14.
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Chaudhry, M., Asad, Z., Sprintson, A., & Hu, J.
(2011).
Efficient CongestionMitigation Using Congestion-Aware Steiner Trees and Network Coding Topologies. VLSI Design.
2011, 1-9.
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Liu, Y., Shelar, R. S., & Hu, J.
(2011).
Simultaneous Technology Mapping and Placement for Delay Minimization. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
30(3), 416-426.
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Shen, W., Cai, Y., Hong, X., & Hu, J.
(2010).
An Effective Gated Clock Tree Design Based on Activity and Register Aware Placement. IEEE Transactions on Very Large Scale Integration Systems.
18(12), 1639-1648.
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Ye, X., Li, P., Zhao, M., Panda, R., & Hu, J.
(2010).
Scalable Analysis of Mesh-Based Clock Distribution Networks Using Application-Specific Reduced Order Modeling. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
29(9), 1342-1353.
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Samanta, R., Hu, J., & Li, P.
(2010).
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks. IEEE Transactions on Very Large Scale Integration Systems.
18(7), 1025-1035.
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Hu, S., Shah, P., & Hu, J.
(2010).
Pattern Sensitive Placement Perturbation for Manufacturability. IEEE Transactions on Very Large Scale Integration Systems.
18(6), 1002-1006.
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Venkataraman, G., Feng, Z., Hu, J., & Li, P.
(2010).
Combinatorial Algorithms for Fast Clock Mesh Optimization. IEEE Transactions on Very Large Scale Integration Systems.
18(1), 131-141.
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Hu, S., & Hu, J.
(2009).
A fast general slew constrained minimum cost buffering algorithm. Microelectronics Journal.
40(10), 1482-1486.
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Shen, W., Cai, Y., Hong, X., Hu, J., & Lu, B.
(2009).
A single layer zero skew clock routing in X architecture. Science China Information Sciences.
52(8), 1466-1475.
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Samanta, R., Venkataraman, G., & Hu, J.
(2009).
Clock Buffer Polarity Assignment for Power Noise Reduction. IEEE Transactions on Very Large Scale Integration Systems.
17(6), 770-780.
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Hu, S., Ketkar, M., & Hu, J.
(2009).
Gate Sizing for Cell-Library-Based Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
28(6), 818-825.
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Hu, S., Ketkar, M., & Hu, J.
(2009).
Gate Sizing for Cell-Library-Based Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
28(6), 818-825.
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Liu, Y., Zhang, T., & Hu, J.
(2009).
Design of Voltage Overscaled Low-Power Trellis Decoders in Presence of Process Variations. IEEE Transactions on Very Large Scale Integration Systems.
17(3), 439-443.
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Liu, Y., Hu, J., & Shi, W.
(2008).
Buffering Interconnect for Multicore Processor Designs. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
27(12), 2183-2196.
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Padmanabhan, U., Wang, J. M., & Hu, J.
(2008).
Robust clock tree routing in the presence of process variations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
27(8), 1385-1397.
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Shen, W., Cai, Y., Hong, X., Hu, J., & Lu, B.
(2008).
Zero skew clock routing in X-architecture based on an improved greedy matching algorithm. Integration.
41(3), 426-438.
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Cao, K., & Hu, J.
(2008).
ASIC design flow considering lithography-induced effects. IET Circuits Devices & Systems.
2(1), 23-29.
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Shen, W., Cai, Y., Hong, X., & Hu, J.
(2008).
Low power gated clock tree driven placement. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.
E91A(2), 595-603.
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Cao, K. e., Hu, J., & Cheng, M.
(2007).
Wire sizing and spacing for lithographic printability and timing optimization. IEEE Transactions on Very Large Scale Integration Systems.
15(12), 1332-1340.
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Hu, S., Alpert, C. J., Hu, J., Karandikar, S. K., Li, Z., Shi, W., & Sze, C. N.
(2007).
Fast algorithms for slew-constrained minimum cost buffering. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
26(11), 2009-2022.
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Hu, S., Li, Q., Hu, J., & Li, P.
(2007).
Utilizing redundancy for timing critical interconnect. IEEE Transactions on Very Large Scale Integration Systems.
15(10), 1067-1080.
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Sze, C. N., Alpert, C. J., Hu, J., & Shi, W.
(2007).
Path-based buffer insertion. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
26(7), 1346-1355.
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Su, B., Chang, Y., & Hu, J.
(2007).
An exact jumper-insertion algorithm for antenna violation avoidance/fixing considering routing obstacles. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
26(4), 719-733.
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Hu, J., & Madden, P. H.
(2007).
Special Issue on the 2006 International Symposium on Physical Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
26(4), 617-618.
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Venkataraman, G., Hu, J., & Liu, F.
(2007).
Integrated placement and skew optimization for rotary clocking. IEEE Transactions on Very Large Scale Integration Systems.
15(2), 149-157.
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Rajaram, A., Lu, B., Hu, J., Mahapatra, R., & Guo, W.
(2006).
Bound for unwanted clock skew due to wire width variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
25(9), 1869-1876.
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Alpert, C. J., Hu, J., Sapatnekar, S. S., & Sze, C. N.
(2006).
Accurate estimation of global buffer delay within a floorplan. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
25(6), 1140-1146.
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Rajaram, A., Hu, J., & Mahapatra, R.
(2006).
Reducing clock skew variability via crosslinks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
25(6), 1176-1182.
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Lu, Y. Q., Sze, C. N., Hong, X. L., Zhou, Q., Cai, Y. C., Huang, L., & Hu, J.
(2005).
Navigating register placement for low power clock network design. IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences.
E88A(12), 3405-3411.
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Chaturvedi, R., & Hu, J.
(2005).
An efficient merging scheme for prescribed skew clock routing. IEEE Transactions on Very Large Scale Integration Systems.
13(6), 750-754.
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Su, H., Hu, J., Sapatnekar, S. S., & Nassif, S. R.
(2004).
A Methodology for the Simultaneous Design of Supply and Signal Networks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
23(12), 1614-1624.
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Alpert, C., Chu, C., Gandham, G., Hrkic, M., Hu, J., Kashyap, C., & Quay, S.
(2004).
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
23(1), 136-141.
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Alpert, C. J., Hu, J., Sapatnekar, S. S., & Villarrubia, P. G.
(2003).
A practical methodology for early buffer and wire resource allocation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
22(5), 573-583.
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Hu, J., Alpert, C. J., Quay, S. T., & Gandham, G.
(2003).
Buffer insertion with adaptive blockage avoidance. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
22(4), 492-498.
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Hu, J., & Sapatnekar, S. S.
(2002).
A timing-constrained simultaneous global routing algorithm. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
21(9), 1025-1036.
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Alpert, C. J., Gandham, G., Hrkic, M., Hu, J., Kahng, A. B., Lillis, J., ... Sullivan, A. J.
(2002).
Buffered Steiner Trees for Difficult Instances. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
21(1), 3-14.
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Su, H., Hu, J., Sapatnekar, S. S., & Nassif, S. R.
(2002).
Congestion-Driven Codesign of Power and Signal Networks **This work was supported in part by the NSF under award CCR-0098117 and by the SRC under contract 99-TJ-714. Design Automation Conference.
64-69.
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Hu, J., & Sapatnekar, S. S.
(2002).
Performance driven global routing through gradual refinement. VLSI Design.
15(3), 595-604.
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Hu, J., & Sapatnekar, S. S.
(2001).
A survey on multi-net global routing for integrated circuits. Integration.
31(1), 1-49.
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Alpert, C. J., Gandham, G., Hu, J., Neves, J. L., Quay, S. T., & Sapatnekar, S. S.
(2001).
Steiner Tree Optimization for Buffers, Blockages, and Bays. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
20(4), 556-562.
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Alpert, C. J., Hu, J., Sapatnekar, S. S., & Villarrubia, P. G.
(2001).
A practical methodology for early buffer and wire resource allocation. Design Automation Conference.
189-194.
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Hu, J., & Sapatnekar, S. S.
(2001).
Performance Driven Global Routing Through Gradual Refinement. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
481-483.
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Hu, J., & Sapatnekar, S. S.
(2000).
Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
19(4), 446-458.
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Hou, H., Hu, J., & Sapatnekar, S. S.
(1999).
Non-Hanan routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
18(4), 436-444.
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Hu, J., & Sapatnekar, S. S.
(1999).
FAR-DS: Full-plane AWE Routing with Driver Sizing. Design Automation Conference.
84-89.
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Hou, H., Hu, J., & Sapatnekar, S. S.
(1999).
Non-Hanan routing. 46(3), 436-444.
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Hu, J., & Sapatnekar, S. S.
(1999).
Simultaneous Buffer Insertion and Non-Hanan Optimization for VLSI interconnect under a higher order AWE model. 133-138.
-
Zhuo, C., Luo, S., Gan, H., Hu, J., & Shi, Z.
(2020).
Noise-Aware DVFS for Efficient Transitions on Battery-Powered IoT Devices. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
39(7), 1498-1510.
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chapter
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Liu, Y., & Hu, J.
(2011).
GPU-Based Parallel Computing for Fast Circuit Optimization. GPU Computing Gems Emerald Edition.
(pp. 365-378).
Elsevier.
-
Hu, J., Li, Z., & Hu, S.
(2008).
Buffer Insertion Basics. Handbook of Algorithms for Physical Design Automation.
Taylor & Francis.
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Hu, J., & Sze, C.
(2008).
Buffering in the Layout Environment. Handbook of Algorithms for Physical Design Automation.
Taylor & Francis.
-
Hu, J., Robins, G., & Sze, C.
(2008).
Timing-Driven Interconnect Synthesis. Handbook of Algorithms for Physical Design Automation.
Taylor & Francis.
-
Hu, J., & Sapatnekar, S. S.
(2001).
Non-Hanan Optimization for Global VLSI Interconnect. Lu, B., Du, D., & Sapatnekar, S. S. (Eds.),
Layout Optimization in VLSI Design.
(pp. 89-123).
Springer Nature.
-
Liu, Y., & Hu, J.
(2011).
GPU-Based Parallel Computing for Fast Circuit Optimization. GPU Computing Gems Emerald Edition.
(pp. 365-378).
Elsevier.
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conference paper
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Li, C., Sapatnekar, S. S., & Hu, J.
(2019).
Fast Mapping-Based High-Level Synthesis of Pipelined Circuits. Proceedings - International Symposium on Quality Electronic Design, ISQED.
33-38.
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Xie, Z., Huang, Y., Fang, G., Ren, H., Fang, S., Chen, Y., & Hu, J.
(2018).
RouteNet: Routability Prediction for Mixed -Size Designs Using Convolutional Neural Network. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
1-8.
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Feng, L., Kudva, P., Da Silva, D., & Hu, J.
(2018).
Exploring Serverless Computing for Neural Network Training. IEEE International Conference on Cloud Computing, CLOUD.
334-341.
-
Huang, L., Hou, I., Sapatnekar, S. S., & Hu, J.
(2018).
Graceful Degradation of Low-Criticality Tasks in Multiprocessor Dual-Criticality Systems. 159-169.
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Jayasankaran, N. G., Borbon, A. S., Sanchez-Sinencio, E., Hu, J., & Rajendran, J.
(2018).
Towards Provably-Secure Analog and Mixed-Signal Locking Against Overproduction. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
1-8.
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Feng, L., Wang, Y., Hu, J., Mak, W., Rajendran, J., & IEEE.
(2017).
Making Split Fabrication Synergistically Secure and Manufacturable. 313-320.
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Feng, L., Wang, Y., Hu, J., Mak, W., Rajendran, J., & IEEE.
(2017).
Making Split Fabrication Synergistically Secure and Manufacturable. 321-328.
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Li, C., Sapatnekar, S. S., & Hu, J.
(2016).
Control Synthesis and Delay Sensor Deployment for Efficient ASV Designs. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
1-7.
-
Snigdha, F. S., Sengupta, D., Hu, J., & Sapatnekar, S. S.
(2016).
Optimal Design of JPEG Hardware Under the Approximate Computing Paradigm. Design Automation Conference.
1-6.
-
Lu, A., He, H., & Hu, J.
(2016).
Proximity Optimization for Adaptive Circuit Design. 91-97.
-
Zhou, H. e., Hu, J., Khatri, S. P., Liu, F., Sze, C., & Yousefi, M. R.
(2016).
GPU Acceleration for Bayesian Control of Markovian Genetic Regulatory Networks. 304-307.
-
Wang, Y., Chen, P. u., Hu, J., & Rajendran, J.
(2016).
The Cat and Mouse in Split Manufacturing. Design Automation Conference.
1-6.
-
Wu, C., Graeb, H., & Hu, J.
(2015).
A Pre-search Assisted ILP Approach to Analog Integrated Circuit Routing. 244-250.
-
Shen, Y., & Hu, J.
(2015).
GPU Acceleration for PCA-Based Statistical Static Timing Analysis. 674-679.
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Wang, J., Shi, C., Sanchez-Sinencio, E., & Hu, J.
(2015).
Built-In Self Optimization for Variation Resilience of Analog Filters. Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI.
656-661.
-
He, H., Wang, J., & Hu, J.
(2015).
Collaborative Gate Implementation Selection and Adaptivity Assignment for Robust Combinational Circuits. Proceedings of the International Symposium on Low Power Electronics and Design.
122-127.
-
Won, J., Gratz, P., Shakkottai, S., & Hu, J.
(2015).
Having Your Cake and Eating It Too: Energy Savings without Performance Loss through Resource Sharing Driven Power Management. Proceedings of the International Symposium on Low Power Electronics and Design.
255-260.
-
Li, C., Luo, W., Sapatnekar, S. S., & Hu, J.
(2015).
Joint Precision Optimization and High Level Synthesis for Approximate Computing. Design Automation Conference.
1-6.
-
Kumar, R., Li, B., Shen, Y., Schlichtmann, U., & Hu, J.
(2015).
Timing Verification for Adaptive Integrated Circuits. Proceedings -Design, Automation and Test in Europe, DATE.
1587-1590.
-
He, H., Yang, G., & Hu, J.
(2014).
Algorithms for Power-Efficient QoS in Application Specific NoCs. Proceedings of the International Symposium on Low Power Electronics and Design.
165-170.
-
Singh, A., & Hu, J.
(2014).
Case Studies on Variation Tolerant and Low Power Design using Planar Asymmetric Double Gate Transistor. The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS. Midwest Symposium on Circuits and Systems.
1021-1024.
-
Won, J., Chen, X. i., Gratz, P., Hu, J., & Soteriou, V.
(2014).
Up By Their Bootstraps: Online Learning in Artificial Neural Networks for CMP Uncore Power Management. Proceedings - International Symposium on High-Performance Computer Architecture.
308-319.
-
Rasheed, S., Gratz, P. V., Shakkottai, S., & Hu, J.
(2014).
STORM: A Simple Traffic-Optimized Router Microarchitecture for Networks-on-Chip. 176-177.
-
Kadjo, D., Kim, H., Gratz, P., Hu, J., & Ayoub, R.
(2013).
Power Gating with Block Migration in Chip-Multiprocessor Last-Level Caches. 93-99.
-
Yang, G., He, H., & Hu, J.
(2013).
Resource Allocation Algorithms for Guaranteed Service in Application-Specific NoCs. 483-486.
-
Chen, X. i., Xu, Z., Kim, H., Gratz, P. V., Hu, J., Kishinevsky, M., Ogras, U., & Ayoub, R.
(2013).
Dynamic voltage and frequency scaling for shared resources in multicore processor designs. 114.
-
Shim, K., & Hu, J.
(2012).
A Low Overhead Built-In Delay Testing with Voltage and Frequency Adaptation for Variation Resilience. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
170-177.
-
Zhao, Q., & Hu, J.
(2012).
Track Assignment Considering Crosstalk-induced Performance Degradation. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
506-507.
-
Chen, X. i., Xu, Z., Kim, H., Gratz, P., Hu, J., Kishinevsky, M., & Ogras, U.
(2012).
In-network Monitoring and Control Policy for DVFS of CMP Networks-on-Chip and Last Level Caches. 43-50.
-
Ozdal, M. M., Burns, S., & Hu, J.
(2011).
Gate Sizing and Device Technology Selection Algorithms for High-Performance Industrial Designs. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
724-731.
-
Chang, Y. W., & Hu, J.
(2011).
Proceedings of the International Symposium on Physical Design: Foreword
-
Shim, K., & Hu, J.
(2011).
Transient and Fine-Grained Voltage Adaptation for Variation Resilience in VLSI Interconnects. Proceedings - International Symposium on Quality Electronic Design, ISQED.
80-86.
-
Huang, Y., Hu, J., & Shi, W.
(2011).
Lagrangian Relaxation for Gate Implementation Selection. 167-174.
-
Chen, X. i., Hu, J., & Xu, N.
(2011).
Regularity-Constrained Floorplanning for Multi-Core Processors. 99-105.
-
Liu, Y., Yang, Y. u., & Hu, J.
(2010).
Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
277-283.
-
Jindal, T., Alpert, C. J., Hu, J., Li, Z., Nam, G., & Winn, C. B.
(2010).
Detecting Tangled Logic Structures in VLSI Netlists. Design Automation Conference.
603-608.
-
Yang, F., Cai, Y., Zhou, Q., & Hu, J.
(2010).
SAT Based Multi-Net Rip-up-and-Reroute for Manufacturing Hotspot Removal. Proceedings -Design, Automation and Test in Europe, DATE.
1369-1372.
-
Shim, K., Hu, J., & Silva-Martinez, J.
(2010).
A Dual-Level Adaptive Supply Voltage System for Variation Resilience. Proceedings - International Symposium on Quality Electronic Design, ISQED.
38-43.
-
Shen, W., Cai, Y., Chen, W., Lu, Y., Zhou, Q., & Hu, J.
(2010).
Useful Clock Skew Optimization under A Multi-corner Multi-mode Design Framework. Proceedings - International Symposium on Quality Electronic Design, ISQED.
62-68.
-
Liu, Y., & Hu, J.
(2010).
A New Algorithm for Simultaneous Gate Sizing and Threshold Voltage Assignment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
223-234.
-
Mekala, V. R., Liu, Y., Ye, X., Hu, J., & Li, P.
(2010).
Accurate clock mesh sizing via sequential quadraticprogramming. 135-142.
-
Wei, Y., Hu, J., Liu, F., & Sapatnekar, S. S.
(2010).
Physical Design Techniques for Optimizing RTA-induced Variations. 745-750.
-
Liu, Y., & Hu, J.
(2009).
GPU-based parallelization for fast circuit optimization. Design Automation Conference.
943-946.
-
Nemade, N., Sprintson, A., & Hu, J.
(2009).
Applications of Network Coding in Global Routing. 55-58.
-
Liu, Y., & Hu, J.
(2009).
A new algorithm for simultaneous gate sizing and threshold voltage assignment. 27-34.
-
Shah, P., & Hu, J.
(2009).
Impact of Lithography-friendly Circuit Layout. 385-388.
-
Chaudhry, M., Asad, Z., Sprintson, A., & Hu, J.
(2009).
Efficient Rerouting Algorithms for Congestion Mitigation. Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI.
43-48.
-
Shah, N., Samanta, R., Zhang, M., Hu, J., & Walker, D.
(2008).
Built-In Proactive Tuning System for Circuit Aging Resilience. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
96-+.
-
Liu, Y., Hu, J., & Shi, W.
(2008).
Multi-Scenario Buffer Insertion in Multi-Core Processor Designs. 15-22.
-
Zhuo, C., Hu, J., Zhao, M., & Chen, K.
(2008).
Power grid analysis and optimization using algebraic multigrid. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
738-751.
-
Ye, X., Zhao, M., Panda, R., Li, P., & Hu, J.
(2008).
Accelerating Clock Mesh Simulation Using MatrixLevel Macromodels and Dynamic Time Step Rounding. 627-632.
-
Samanta, R., Venkataraman, G., Shah, N., & Hu, J.
(2008).
Elastic Timing Scheme for Energy-Efficient and Robust Performance. 537-542.
-
Samanta, R., Hu, J., & Li, P.
(2008).
Discrete Buffer and Wire Sizing for Link-based Non-tree Clock Networks. 175-181.
-
Varadan, S., Wang, J., & Hu, J.
(2008).
Handling Partial Correlations in Yield Prediction. 543-548.
-
Wang, Y., Zhou, Q., Cai, Y., Hu, J., Hong, X., & Bian, J.
(2008).
Low Power Clock Buffer Planning Methodology in F-D Placement for Large Scale Circuit Design*This work was supported partly by National Science Foundation of China (90407005, 90607001 and 60776026), and project of 3-D floorplanning and placement of Intel Corporation. 370-375.
-
Hu, S., & Hu, J.
(2007).
A new fast slew buffering algorithm without input slew assumptions. 93-+.
-
Zhuo, C., Zhang, H., Samanta, R., Hu, J., & Chen, K.
(2007).
Modeling, Optimization and Control of Rotary Traveling-Wave Oscillator. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
476-480.
-
Hu, S., & Hu, J.
(2007).
Unified adaptivity optimization of clock and logic signals. ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS.
125-130.
-
Hu, S., Ketkar, M., & Hu, J.
(2007).
Gate sizing for cell library-based designs. Design Automation Conference.
847-+.
-
Liu, Y., Zhang, T., & Hu, J.
(2007).
Soft clock skew scheduling for variation-tolerant signal processing circuits: A case study of viterbi decoders. 749-+.
-
Cao, K. e., Hu, J., & Cheng, M.
(2007).
Wire sizing and spacing for lithographic printability optimization. Proceedings of SPIE.
652111-652111-9.
-
Venkataraman, G., Hu, J., & Liu, F. Y.
(2007).
Integrated placement and skew optimization for rotary clocking. IEEE Transactions on Very Large Scale Integration Systems.
149-158.
-
Jiang, Z., Hu, S., Hu, J., & Shi, W.
(2007).
An efficient alorintham for RLC buffer insertion. Proceedings - International Symposium on Quality Electronic Design, ISQED.
171-+.
-
Hu, S., & Hu, J.
(2007).
Pattern Sensitive Placement For Manufacturability. 27-34.
-
Liu, B., Kahng, A. B., Xu, X. u., Hu, J., & Venkataraman, G.
(2007).
A global minimum clock distribution network augmentation algorithm for guaranteed clock skew yield. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
25-+.
-
Venkataraman, G., & Hu, J.
(2007).
A placement methodology for robust clocking. Proceedings of the IEEE International Conference on VLSI Design.
881-+.
-
Kim, M., & Hu, J.
(2006).
Associative skew clock routing for difficult instances. Proceedings -Design, Automation and Test in Europe, DATE.
760-+.
-
Shen, W., Cai, Y., Hu, J., Hong, X., & Lu, B.
(2006).
High performance clock routing in X-architecture. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
2081-2084.
-
Samanta, R., Venkataraman, G., & Hu, J.
(2006).
Clock Buffer Polarity Assignment for Power Noise Reduction**This work is partially supported by Semiconductor Research Corporation under contract 2004-TJ-1205. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
558-562.
-
Venkataraman, G., Feng, Z., Hu, J., & Li, P.
(2006).
Combinatorial Algorithms for Fast Clock Mesh Optimization* *This work was supported in part by SRC under contract number 2004-TJ-1205 and 2006-TJ-1416. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
563-567.
-
Zhuo, C., Hu, J., Zhao, M., & Chen, K.
(2006).
Fast Decap Allocation Based on Algebraic Multigrid. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
107-111.
-
Cao, K. e., Dobre, S., & Hu, J.
(2006).
Standard cell characterization considering lithography induced variations. Design Automation Conference.
801-804.
-
Su, B. Y., Chang, Y. W., & Hu, J.
(2006).
An optimal jumper insertion algorithm for antenna avoidance/fixing on general routing trees with obstacles. 56-63.
-
Padmanabhan, U., Wang, J. M., & Hu, J.
(2006).
Statistical clock tree routing for robustness to process variations. 149-156.
-
Wu, D., Hu, J., & Mahapatra, R. N.
(2006).
Antenna avoidance in layer assignment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
734-738.
-
Jiang, Z., Hu, S., Hu, J., Li, Z., & Shi, W.
(2006).
A New RLC Buffer Insertion Algorithm. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
553-557.
-
Hu, S., Alpert, C. J., Hu, J., Karandikar, S., Li, Z., Shi, W., & Sze, C. N.
(2006).
Fast algorithms for slew constrained minimum cost buffering. Design Automation Conference.
308-313.
-
Hu, S., Li, Q., Hu, J., & Li, P.
(2006).
Steiner network construction for timing critical nets. Design Automation Conference.
379-384.
-
Zhuo, C., Hu, J., & Chen, K.
(2006).
An improved AMG-based method for fast power grid analysis. Proceedings - International Symposium on Quality Electronic Design, ISQED.
290-+.
-
Feng, Z., Li, P., & Hu, J.
(2006).
Efficient model update for general link-insertion networks. Proceedings - International Symposium on Quality Electronic Design, ISQED.
43-+.
-
Huang, L., Cai, Y., Zhou, Q., Hong, X., Hu, J., & Lu, Y.
(2005).
Clock network minimization methodology based on incremental placement. 99-102.
-
Rajaram, A., Pan, D. Z., & Hu, J.
(2005).
Improved algorithms for link-based non-tree Clock Networks for skew variability reduction. 55-62.
-
Cao, K. e., Dhawan, P., & Hu, J.
(2005).
Library cell layout with Alt-PSM compliance and composability. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
216-219.
-
Li, Z., Sze, C. N., Alpert, C. J., Hu, J., & Shi, W.
(2005).
Making fast buffer insertion even faster via approximation techniques. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
13-18.
-
Lu, Y., Sze, C. N., Hong, X., Zhou, Q., Cai, Y., Huang, L., & Hu, J.
(2005).
Navigating registers in placement for clock network minimization. Design Automation Conference.
176-181.
-
Sze, C. N., Alpert, C. J., Hu, J., & Shi, W. P.
(2005).
Path based buffer insertion. Design Automation Conference.
509-514.
-
Lu, Y., Sze, C. N., Hong, X., Zhou, Q., Cai, Y., Huang, L., & Hu, J.
(2005).
Register placement for low power clock network. 588-593.
-
Wu, D. i., Hu, J., & Mahapatra, R.
(2005).
Coupling aware timing optimization and antenna avoidance in layer assignment. 20-27.
-
Wu, D., Venkataraman, G., Hu, J., Li, Q. Y., & Mahapatra, R.
(2005).
DiCER: Distributed and cost-effective redundancy for variation tolerance. ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS.
393-397.
-
Venkataraman, G., Jayakumar, N., Hu, J., Li, P., Khatri, S., Rajaram, A., McGuinness, P., & Alpert, C.
(2005).
Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS.
592-596.
-
Venkataraman, G., Sze, C. N., & Hu, J.
(2005).
Skew scheduling and clock routing for improved tolerance to process variations. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
594-599.
-
Alpert, C. J., Hrkic, M., Hu, J., & Quay, S. T.
(2004).
Fast and flexible buffer trees that navigate the physical layout environment. Design Automation Conference.
24-29.
-
Cao, K., Hu, J., & Cheng, M.
(2004).
Layout modification for library cell Alt-PSM composability. Proceedings of SPIE.
253-259.
-
Alpert, C. J., Gandham, G., Hrkic, M., Hu, J., Quay, S. T., & Sze, C. N.
(2004).
Porosity-aware buffered steiner tree construction. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
517-526.
-
Rajaram, A., Hu, J., & Mahapatra, R.
(2004).
Reducing clock Skew variability via cross links. Design Automation Conference.
18-23.
-
Sze, C. N., Hu, J., & Alpert, C. J.
(2004).
A place and route aware buffered steiner tree construction. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
355-360.
-
Alpert, C. J., Hu, J., Sapatnekar, S. S., & Sze, C. N.
(2004).
Accurate Estimation of Global Buffer Delay within a Floorplan. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
706-711.
-
Chaturvedi, R., & Hu, J.
(2004).
Buffered clock tree for high quality IC design. 381-386.
-
Seth, V., Zhao, M., & Hu, J.
(2004).
Exploiting level sensitive latches in wire pipelining. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
283-290.
-
Wu, D., Hu, J., Mahapatra, R., & Zhao, M.
(2004).
Layer assignment for crosstalk risk minimization. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
159-162.
-
Alpert, C. J., Gandham, G., Hrkic, M., Hu, J., & Quay, S. T.
(2003).
Porosity aware buffered steiner tree construction. 158-165.
-
Lu, B., Hu, J., Ellis, G., & Su, H.
(2003).
Process variation aware clock tree routing. 174-181.
-
Rajaram, A., Lu, B., Guo, W., Mahapatra, R., & Hu, J.
(2003).
Analytical bound for unwanted clock skew due to wire width variation. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
401-406.
-
Chaturvedi, R., & Hu, J.
(2003).
A simple yet effective merging scheme for prescribed-skew clock routing. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
282-287.
-
Hu, J., Alpert, C. J., Quay, S. T., & Gandham, G.
(2002).
Buffer insertion with adaptive blockage avoidance. 92-97.
-
Alpert, C., Chu, C., Gandham, G., Hrkic, M., Hu, J., Kashyap, C., & Quay, S.
(2002).
Simultaneous driver sizing and buffer insertion using a delay penalty estimation technique. 104-109.
-
Alpert, C. J., Hrkic, M., Hu, J., Kahng, A. B., Lillis, J., Liu, B., ... Villarrubia, P.
(2001).
Buffered Steiner trees for difficult instances. 4-9.
-
Alpert, C. J., Gandham, G., Hu, J., Neves, J. L., Quay, S. T., & Sapatnekar, S. S.
(2001).
Steiner tree optimization for buffers. Blockages and bays. 399-402.
-
Hu, J., & Sapatnekar, S. S.
(2000).
A timing-constrained algorithm for simultaneous global routing of multiple nets. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
99-103.
-
Li, C., Sapatnekar, S. S., & Hu, J.
(2019).
Fast Mapping-Based High-Level Synthesis of Pipelined Circuits. Proceedings - International Symposium on Quality Electronic Design, ISQED.
33-38.
Research
principal investigator on
- RTML: Small: Real-Time Model-Based Bayesian Reinforcement Learning awarded by National Science Foundation - (Arlington, Virginia, United States) 2019 - 2022
- STARSS: Small: Collaborative: Physical Design for Secure Split Manufacturing of ICs awarded by National Science Foundation - (Arlington, Virginia, United States) 2016 - 2020
- SHF:Small:Collaborative Research: Variation-Resilient VLSI Systems with Controlled Approximation awarded by National Science Foundation - (Arlington, Virginia, United States) 2015 - 2019
- Design Automation for Cost-Effective Implementation of Adaptive Integrated Circuits awarded by National Science Foundation - (Arlington, Virginia, United States) 2013 - 2017
co-principal investigator on
- CPS: Medium: Real-Time Learning and Control of Stochastic Nanostructure Growth Processes Through in situ Dynamic Imaging awarded by Directorate for Engineering - (Arlington, Virginia, United States) 2021 - 2023
- SHF:Small: OSCARS: Optimizing Self-Configurable Analog ICs for Reliability and Security awarded by National Science Foundation - (Arlington, Virginia, United States) 2018 - 2021
Teaching
teaching activities
- CSCE491 Hnr-research Instructor
- CSCE684 Professional Internship Instructor
- CSCE685 Directed Studies Instructor
- CSCE689 Sptp:formal Verification Instructor
- CSCE691 Research Instructor
- ECEN403 Electrical Design Lab I Instructor
- ECEN404 Electrical Design Lab Ii Instructor
- ECEN428 Fpga Info Processing Systems Instructor
- ECEN449 Microprocsr Sys Dsgn Instructor
- ECEN468 Advanced Digital System Design Instructor
- ECEN489 Sptp: Fpga Info Proc Sys Instructor
- ECEN489 Sptp:fpga Info Proc Sys Instructor
- ECEN491 Research Instructor
- ECEN684 Professional Internship Instructor
- ECEN684 Professional Internship: In-ab Instructor
- ECEN685 Directed Studies Instructor
- ECEN687 Intro Vlsi Desn Auto Instructor
- ECEN689 Sptp: Dependable Learning Syst Instructor
- ECEN689 Sptp: Fpga Info Proc Sys Instructor
- ECEN689 Sptp:fpga Info Proc Sys Instructor
- ECEN691 Research Instructor
- ECEN719 Advanced Digital System Design Instructor
- ECEN722 Field Program Gate Arrays Ips Instructor
- ECEN749 Microprocessor Systems Design Instructor
Works By Students
chaired theses and dissertations
-
Belsare, Aditya Sanjay (2014-08). Sparse LU Factorization for Large Circuit Matrices on Heterogenous Parallel Computing Platforms.
-
Bhosekar, Shilpa (2018-08). Best Effort Minimal Routing for Fly-Over: A Light Weight Distributed Mechanism for Energy Efficient Network-On-Chip.
-
Chang, Chi-Yu (2012-08). Analytical Layer Planning for Nanometer VLSI Designs.
-
Chen, Pu (2016-12). Security Attack Models for Split Manufacturing of Integrated Circuits.
-
Chen, Xi (2013-05). Physical Planning and Uncore Power Management for Multi-Core Processors.
-
Gangrade, Rohit (2016-04). GPU Based Acceleration of SystemC and Transaction Level Models for MPSOC Simulation.
-
Gao, Zhuoyang (2015-12). Comparative Study on Performance and Variation Tolerance of Low Power Circuit.
-
Gope, Dibakar (2011-08). Maximizing Crosstalk-Induced Slowdown During Path Delay Test.
-
He, Hao (2016-11). Resource Management Algorithms for Computing Hardware Design and Operations: From Circuits to Systems.
-
Huang, Yi-Le (2010-12). An Improved Lagrangian Relaxation Method for VLSI Combinational Circuit Optimization.
-
Irukula, Shivaram (2015-08). Reinforcement Learning Based Controller For Precision Irrigation.
-
Jindal, Tanuj (2010-08). Detecting Tangled Logic Structures in VLSI Netlists.
-
Kansal, Rohan (2013-08). A Pure STT-MRAM Design for High-bandwidth Low-power On-chip Interconnects.
-
Kumar, Rohit (2014-08). Timing Verification of Adaptive Integrated Circuits.
-
Li, Chaofan (2018-05). Synthesis Techniques for Power-Efficient Integrated Circuits.
-
Lu, Ang (2015-12). Proximity Optimization for Adaptive Circuit Design.
-
Ni, Ruixiao (2014-05). On the Effectiveness of Source Throttling for Networks-on-Chip in Chip Multiprocessor Designs.
-
Panda, Reena (2011-12). A Branch-Directed Data Cache Prefetching Technique for Inorder Processors.
-
Puli, Ramprakash Reddy (2018-05). Active Routing: Compute on the Way for Near-Data Processing.
-
Ramakrishnan, Sundararajan (2010-08). Case Studies on Clock Gating and Local Routign for VLSI Clock Mesh.
-
Rasheed, Farah (2013-12). Artificial Neural Network Circuit for Spectral Pattern Recognition.
-
Rasheed, Shalimar (2014-05). A Network-on-Chip Router for Low-Latency and High-Throughput Dimension-Order Routing.
-
Sharma, Prabal (2013-08). A Branch Predictor Directed Data Cache Prefetcher for Out-of-order and Multicore Processors.
-
Shen, Yiren (2016-05). Parallel Acceleration for Timing Analysis and Optimization of Adaptive Integrated Circuits.
-
Shim, Kyu-Nam 1978- (2012-12). Voltage and Timing Adaptation for Variation and Aging Tolerance in Nanometer VLSI Circuits.
-
Shrija, . (2016-12). A Reconfigurable Approximate JPEG Encoder Implemented On FPGA Platform.
-
Singh, Amrinder (2010-08). Case Studies on Variation Tolerant and Low Power Design Using Planar Asymmetric Double Gate Transistor.
-
Sun, Lijia (2018-08). Modeling and Control Techniques in Smart Systems.
-
Tsai, Jung-Tai (2013-08). VLSI Interconnect Optimization Considering Non-uniform Metal Stacks.
-
Wang, Jiafan (2017-08). Adaptive Integrated Circuit Design for Variation Resilience and Security.
-
Won, Jae Yeon (2015-08). Dynamic Voltage and Frequency Scaling Techniques for Chip Multiprocessor Designs.
-
Wu, Chia-Yu (2015-08). A Pre-Search Assisted ILP Approach to Analog Integrated Circuit Routing.
-
Xu, Zheng (2013-08). Control Techniques for Uncore Power Mangement in Chip Multiprocessor Designs.
-
Yang, Gongming (2014-05). NoC Resource Allocation Based on Physical Design Techniques.
-
Yang, Yu (2011-05). Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems.
-
Zhai, Sitong (2015-08). A Layer Centric VLSI Physical Design Methodology Considering Non-uniform Metal Stacks.
-
Zhao, Qiong (2012-05). Track Assignment Considering Crosstalk-Induced Performance Degradation.
Background
education and training
- Ph.D. in Electrical Engineering, University of Minnesota - (Minneapolis, Minnesota, United States) 2001
- M.S. in Physics, Zhejiang University - (Hangzhou, Zhejiang, China) 1997
- B.S. in Optical Engineering, Zhejiang University - (Hangzhou, Zhejiang, China) 1990
awards and honors
Contact
first name
- Jiang
has last name
- Hu
mailing address
-
Texas A&M University
Electrical Engineering
3128 TAMU
College Station, TX 77843-3128
USA
Other
- jianghu@tamu.edu