Dynamic voltage and frequency scaling for shared resources in multicore processor designs Conference Paper uri icon

abstract

  • As the core count in processor chips grows, so do the on-die, shared resources such as on-chip communication fabric and shared cache, which are of paramount importance for chip performance and power. This paper presents a method for dynamic voltage/frequency scaling of networks-on-chip and last level caches in multicore processor designs, where the shared resources form a single voltage/frequency domain. Several new techniques for monitoring and control are de- veloped, and validated through full system simulations on the PARSEC benchmarks. These techniques reduce energy- delay product by 56% compared to a state-of-the-art prior work. Copyright 2013 ACM.

name of conference

  • the 50th Annual Design Automation Conference

published proceedings

  • 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC)

author list (cited authors)

  • Chen, X. i., Xu, Z., Kim, H., Gratz, P. V., Hu, J., Kishinevsky, M., Ogras, U., & Ayoub, R.

citation count

  • 45

complete list of authors

  • Chen, Xi||Xu, Zheng||Kim, Hyungjun||Gratz, Paul V||Hu, Jiang||Kishinevsky, Michael||Ogras, Umit||Ayoub, Raid

publication date

  • January 1, 2013 11:11 AM