Accurate estimation of global buffer delay within a floorplan Conference Paper uri icon

abstract

  • Closed formed expressions for buffered interconnect delay approximation have been around for some time. However, previous approaches assume that buffers are free to be placed anywhere. In practice, designs frequently have large blocks that make the ideal buffer insertion solution unrealizable. The theory of [12] is extended to show how one can model the blocks into a simple delay estimation technique that applies both to two-pin and to multi-pin nets. Even though the formula uses one buffer type, it shows remarkable accuracy in predicting delay when compared to an optimal realizable buffer insertion solution. Potential applications include wire planning, timing analysis during floorplanning or global routing. Our experiments show that our approach accurately predicts delay when compared to constructing an realizable buffer insertion with multiple buffer types. 2004 IEEE.

name of conference

  • ICCAD 2004. International Conference on Computer Aided Design

published proceedings

  • IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

author list (cited authors)

  • Alpert, C. J., Jiang Hu, .., Sapatnekar, S. S., & Sze, C. N.

citation count

  • 13

complete list of authors

  • Alpert, CJ||Sapatnekar, SS||Sze, CN

publication date

  • January 2004

publisher