publication venue for
- Towards provably-secure analog and mixed-signal locking against overproduction 2018
- Front-end-of-line attacks in split manufacturing 2017
- CamoPerturb: Secure IC camouflaging for minterm protection 2016
- Security of neuromorphic computing: Thwarting learning attacks using memristor's obsolescence effect 2016
- Shielding and securing integrated circuits with sensors 2015
- Hardware security: Threat models and metrics 2013
- Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems 2010
- Introduction to GPU programming for EDA 2009
- Nonvolatile memristor memory: Device characteristics and design implications 2009
- SRAM Dynamic Stability: Theory, Variability and Analysis 2008
- Modeling, Optimization and Control of Rotary Traveling-Wave Oscillator 2007
- Unified Adaptivity Optimization of Clock and Logic Signals 2007
- Impedance Extraction for 3-D Structures with Multiple Dielectrics Using Preconditioned Boundary Element Method 2007
- Network coding for routability improvement in VLSI 2006
- A New RLC Buffer Insertion Algorithm 2006
- Clock Buffer Polarity Assignment for Power Noise Reduction**This work is partially supported by Semiconductor Research Corporation under contract 2004-TJ-1205. 2006
- Combinatorial Algorithms for Fast Clock Mesh Optimization* *This work was supported in part by SRC under contract number 2004-TJ-1205 and 2006-TJ-1416. 2006
- Fast Decap Allocation Based on Algebraic Multigrid 2006
- Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects 2006
- A METAL and VIA Maskset Programmable VLSI Design Methodology using PLAs 2004
- A Novel Clock Distribution and Dynamic De-Skewing Methodology 2004
- Accurate Estimation of Global Buffer Delay within a Floorplan 2004
- Exploiting Level Sensitive Latches in Wire Pipelining 2004
- M-Trie: An Efficient Approach To On-Chip Logic Minimization 2004
- Analytical Bound for Unwanted Clock Skew Due to Wire Width Variation 2003
- Addressing the timing closure problem by integrating logic optimization and placement 2001
- A timing-constrained algorithm for simultaneous global routing of multiple nets 2000
- Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric 2000
- Optimal algorithm for area minimization of slicing floorplans 1995