publication venue for
- Front-End-of-Line Attacks in Split Manufacturing 2017
- CamoPerturb 2016
- Security of neuromorphic computing 2016
- Shielding and Securing Integrated Circuits with Sensors 2014
- Hardware Security: Threat Models and Metrics 2013
- Clustering-Based Simultaneous Task and Voltage Scheduling for NoC Systems 2010
- Introduction to GPU programming for EDA 2009
- Nonvolatile memristor memory: Device characteristics and design implications 2009
- SRAM Dynamic Stability: Theory, Variability and Analysis 2008
- Modeling, Optimization and Control of Rotary Traveling-Wave Oscillator 2007
- Clock Buffer Polarity Assignment for Power Noise Reduction**This work is partially supported by Semiconductor Research Corporation under contract 2004-TJ-1205. 2006
- Combinatorial Algorithms for Fast Clock Mesh Optimization* *This work was supported in part by SRC under contract number 2004-TJ-1205 and 2006-TJ-1416. 2006
- Fast Decap Allocation Based on Algebraic Multigrid 2006
- Network Coding for Routability Improvement in VLSI 2006
- A New RLC Buffer Insertion Algorithm 2006
- Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects 2006
- A METAL and VIA maskset programmable VLSI design methodology using PLAs 2004
- A novel clock distribution and dynamic de-skewing methodology 2004
- Accurate Estimation of Global Buffer Delay within a Floorplan 2004
- Exploiting level sensitive latches in wire pipelining 2004
- m-Trie: An efficient approach to on-chip logic minimization 2004
- Analytical bound for unwanted clock skew due to wire width variation 2003
- Addressing the timing closure problem by integrating logic optimization and placement 2001
- A timing-constrained algorithm for simultaneous global routing of multiple nets 2000
- Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric 2000
- Optimal algorithm for area minimization of slicing floorplans 1995