Clock Buffer Polarity Assignment for Power Noise Reduction Conference Paper uri icon

abstract

  • Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assignment algorithms are proposed: (1) partitioning, (2) 2-coloring on minimum spanning tree and (3) recursive min-matching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 44% and 54% respectively. Copyright 2006 ACM.

name of conference

  • 2006 IEEE/ACM International Conference on Computer Aided Design

published proceedings

  • 2006 IEEE/ACM International Conference on Computer Aided Design

author list (cited authors)

  • Samanta, R., Venkataraman, G., & Hu, J.

citation count

  • 2

complete list of authors

  • Samanta, Rupak||Venkataraman, Ganesh||Hu, Jiang

publication date

  • November 2006

publisher