m-Trie: An efficient approach to on-chip logic minimization Conference Paper

abstract

• Boolean logic minimization is being increasingly applied to new applications which demands very fast and frequent minimization services. These applications typically offer very limited computing and memory resources rendering the traditional logic minimizers ineffective. We present a new approximate logic minimization algorithm based on ternary trie. We compare its performance with Espresso-II and ROCM logic minimizers for routing table compaction and demonstrate that it is 100 to 1000 times faster and can run with a data memory as little as 16KB. It is also found that proposed approach can support up to 25000 incremental updates per seconds positioning itself as an ideal on-chip logic minimization algorithm. 2004 IEEE.

name of conference

• IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.

authors

• Mahapatra, Rabinarayan

published proceedings

• ICCAD-2004: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, IEEE/ACM DIGEST OF TECHNICAL PAPERS

author list (cited authors)

• Ahmad, S., & Mahapatra, R.

citation count

• 2

complete list of authors

• Ahmad, S||Mahapatra, R

publication date

• January 2004

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers  Journal

keywords

• 40 Engineering
• 4009 Electronics, Sensors And Digital Hardware
• 46 Information And Computing Sciences

Digital Object Identifier (DOI)

• 10.1109/ICCAD.2004.1382613

International Standard Book Number (ISBN) 10

• 0-7803-8702-3

start page

• 428

end page

• 435

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ficcad.2004.1382613