Combinatorial Algorithms for Fast Clock Mesh Optimization* *This work was supported in part by SRC under contract number 2004-TJ-1205 and 2006-TJ-1416.
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We present a fast and efficient combinatorial algorithm to simultaneously identify the candidate locations as well as the sizes of the buffers driving a clock mesh. Due to the high redundancy, a mesh architecture offers high tolerance towards variation in the clock skew. However, such a redundancy comes at the expense of mesh wire length and power dissipation. Based on survivable network theory, we formulate the problem to reduce the clock mesh by retaining only those edges that are critical to maintain redundancy. Such a formulation offers designer the option to trade-off between power and tolerance to process variations. Experimental results indicate that our techniques can result in power savings up to 28% with less than 4% delay penalty. Copyright 2006 ACM.
author list (cited authors)
Venkataraman, G., Feng, Z., Hu, J., & Li, P.