A metal and via maskset programmable VLSI design methodology using PLAs
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In recent times there has been a substantial increase in the cost and complexity of fabricating a VLSI chip. The lithography masks themselves can cost between $1M and $3M. It is conjectured that due to these increasing costs, the number of ASIC starts in the last few years has declined. In this paper, we address this problem by using an array of dynamic PLAs which require only METAL and VIA mask customization in order to implement a new design. This would allow several similar-sized designs to share the same base set of masks (right up to the metal layers) and only have different METAL and VIA masks. We have implemented our methodology for both combinational and sequential designs, and demonstrate that our approach strikes a reasonable compromise between ASIC and field programmable design methodologies in terms of placed-and-routed area and delay. Our method has a 2.89 (3.58) delay overhead and a 4.96 (3.44) area overhead compared to standard cells for combinational (sequential) designs. 2004 IEEE.
name of conference
ICCAD 2004. International Conference on Computer Aided Design
IEEE/ACM International Conference on Computer Aided Design, 2004. ICCAD-2004.
author list (cited authors)
Jayakumar, N., & Khatri, S. P.
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