A timing-constrained algorithm for simultaneous global routing of multiple nets Conference Paper uri icon


  • 2000 IEEE. In this paper we propose a new approach for VLSI interconnect global routing that can optimize both congestion and delay, which are often competing objectives. Our approach provides a general framework that may use any single-net routing algorithm and any delay model in global routing. It is based on the observation that there are several routing topology flexibilities under timing constraints. These flexibilities are exploited for congestion reduction through a network flow based hierarchical bisection and assignment process. Experimental results on benchmark circuits are quite promising.

name of conference

  • IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140)

published proceedings

  • 2019 IEEE/ACM International Conference on Computer-Aided Design (ICCAD)

author list (cited authors)

  • Hu, J., & Sapatnekar, S. S.

citation count

  • 35

complete list of authors

  • Hu, Jiang||Sapatnekar, SS

publication date

  • January 2000