Reducing clock skew variability via cross links Conference Paper uri icon


  • Increasingly significant variational effects present a great challenge for delivering desired clock skew reliably. Non-tree clock network has been recognized as a promising approach to overcome the variation problem. Existing non-tree clock routing methods are restricted to a few simple or regular structures, and often consume excessive amount of wirelength. In this paper, we suggest to construct a low cost non-tree clock network by inserting cross links in a given clock tree. The effects of the link insertion on clock skew variability are analyzed. Based on the analysis, we propose two link insertion schemes that can quickly convert a clock tree to a non-tree with significantly lower skew variability and very limited wirelength increase. In these schemes, the complicated non-tree delay computation is circumvented. Further, they can be applied to the recently popular non-zero skew routing easily. Experimental results on benchmark circuits show that this approach can achieve significant skew variability reduction with less than 2% increase of wirelength.

name of conference

  • the 41st annual conference

published proceedings

  • Proceedings of the 41st annual conference on Design automation - DAC '04

author list (cited authors)

  • Rajaram, A., Hu, J., & Mahapatra, R.

citation count

  • 66

complete list of authors

  • Rajaram, Anand||Hu, Jiang||Mahapatra, Rabi

publication date

  • January 2004