Analytical bound for unwanted clock skew due to wire width variation Academic Article uri icon


  • Under modern very large-scale integrated technology, process variations greatly affect circuit performance, especially clock skew, which is very timing sensitive. Unwanted skew due to process variation forms a bottleneck, preventing further improvement on clock frequency. Impact from intrachip interconnect variation is becoming remarkable and is difficult to be modeled efficiently due to its distributive nature. Through wire shaping analysis, the authors establish an analytical bound for the unwanted skew due to wire width variation, which is a nonnegligible factor among interconnect variations. Experimental results on benchmark circuits show that this bound is safer, tighter, and computationally faster than similar existing approach. 2006 IEEE.

published proceedings

  • IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

author list (cited authors)

  • Rajaram, A., Bing Lu, .., Jiang Hu, .., Mahapatra, R., & Wei Guo.

citation count

  • 0

complete list of authors

  • Rajaram, A||Mahapatra, R

publication date

  • September 2006