HR job title
- Professor
- Contact Info
- 1 979 845 5787
- Websites
Mahapatra, Rabinarayan Professor - Term Appointment
Positions
- Professor - Term Appointment, Computer Science and Engineering, College of Engineering
My principal areas of research are Embedded Systems, Systems on Chip, Low-power system design, and Data Analytic Codesign.
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Overview
Publications
selected publications
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academicarticle
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Dang, D., Chittamuru, S., Pasricha, S., Mahapatra, R., & Sahoo, D.
(2021).
BPLight-CNN: A Photonics-based Backpropagation Accelerator for Deep Learning
-
Rasheed, A. A., Mahapatra, R. N., & Hamza-Lup, F. G.
(2020).
Adaptive Group-Based Zero Knowledge Proof-Authentication Protocol in Vehicular Ad Hoc Networks. IEEE Transactions on Intelligent Transportation Systems.
21(2), 867-881.
-
Dass, J., Narawane, Y., Mahapatra, R. N., & Sarin, V.
(2020).
Distributed Training of Support Vector Machine on a Multiple-FPGA System. IEEE Transactions on Computers.
69(7), 1015-1026.
-
Dass, J., Sarin, V., & Mahapatra, R. N.
(2019).
Fast and Communication-Efficient Algorithm for Distributed Support Vector Machine Training. 30(5), 1065-1076.
-
Mandal, S., Bhojwani, P., Mohanty, S., & Mahapatra, R.
(2019).
IntellBatt: The Smart Battery. Computer.
PP(99), 1-1.
-
Chittamuru, S., Dang, D., Pasricha, S., & Mahapatra, R.
(2018).
BiGNoC: Accelerating Big Data Computing with Application-Specific Photonic Network-on-Chip Architectures. IEEE Transactions on Parallel and Distributed Systems.
29(11), 2402-2415.
-
Tang, J., Xi, L., & Mahapatra, R.
(2018).
An open-loop system design for deep space signal processing applications. Acta Astronautica.
147, 259-272.
-
Tang, J., Mahapatra, R. N., Meng, Q., & Xia, L.
(2018).
Hybrid algorithm for accumulated error suppression in openloop Doppler receiver. IET Communications.
12(7), 765-770.
-
Rasheed, A., & Mahapatra, R. N.
(2012).
The Three-Tier Security Scheme in Wireless Sensor Networks with Mobile Sinks. IEEE Transactions on Parallel and Distributed Systems.
23(5), 958-965.
-
Yu, H., & Mahapatra, R. N.
(2011).
A Power and Throughput-Efficient Packet Classifier with n Bloom Filters. IEEE Transactions on Computers.
60(8), 1182-1193.
-
Rasheed, A., & Mahapatra, R.
(2011).
Key Predistribution Schemes for Establishing Pairwise Keys with a Mobile Sink in Sensor Networks. IEEE Transactions on Parallel and Distributed Systems.
22(1), 176-184.
-
Kim, Y., Mahapatra, R. N., & Choi, K.
(2010).
Design Space Exploration for Efficient Resource Utilization in Coarse-Grained Reconfigurable Architecture. IEEE Transactions on Very Large Scale Integration Systems.
18(10), 1471-1482.
-
Mandal, S. K., & Mahapatra, R.
(2010).
PowerAntz: Ant behavior inspired power budget distribution scheme for Network-on-Chip systems. Microelectronics Journal.
41(8), 523-531.
-
Mandal, S. K., Mahapatra, R. N., Bhojwani, P. S., & Mohanty, S. P.
(2010).
IntellBatt: Toward a Smarter Battery. Computer.
43(3), 67-71.
-
Kim, Y., & Mahapatra, R. N.
(2010).
Dynamic Context Compression for Low-Power Coarse-Grained Reconfigurable Architecture. IEEE Transactions on Very Large Scale Integration Systems.
18(1), 15-28.
-
Kim, Y., Mahapatra, R. N., Park, I., & Choi, K.
(2009).
Low Power Reconfiguration Technique for Coarse-Grained Reconfigurable Architecture. IEEE Transactions on Very Large Scale Integration Systems.
17(5), 593-603.
-
Kougianos, E., Mohanty, S. P., & Mahapatra, R. N.
(2009).
Hardware assisted watermarking for multimedia. Computers and Electrical Engineering.
35(2), 339-358.
-
Dechev, D., Mahapatra, R., & Stroustrup, B.
(2008).
Practical and Verifiable C++ Dynamic Cast for Hard Real-Time Systems. Journal of Computing Science and Engineering.
2(4), 375-393.
-
Bhojwani, P. S., & Mahapatra, R. N.
(2008).
Robust Concurrent Online Testing of Network-on-Chip-Based SoCs. IEEE Transactions on Very Large Scale Integration Systems.
16(9), 1199-1209.
-
Acharya, S., & Mahapatra, R. N.
(2008).
A Dynamic Slack Management Technique for Real-Time Distributed Embedded Systems. IEEE Transactions on Computers.
57(2), 215-230.
-
Nolen, J. M., & Mahapatra, R. N.
(2008).
Time-Division-Multiplexed Test Delivery for NoC Systems. IEEE Design and Test.
25(1), 44-51.
-
Ahmad, S., & Mahapatra, R. N.
(2007).
An Efficient Approach to On-Chip Logic Minimization. IEEE Transactions on Very Large Scale Integration Systems.
15(9), 1040-1050.
-
Nolen, J., & Mahapatra, R.
(2007).
Time-Division- Multiplexed test delivery for NoC systems. IEEE Design and Test.
24(99), x3-x3.
-
Rajaram, A., Lu, B., Hu, J., Mahapatra, R., & Guo, W.
(2006).
Bound for unwanted clock skew due to wire width variation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
25(9), 1869-1876.
-
Rajaram, A., Hu, J., & Mahapatra, R.
(2006).
Reducing clock skew variability via crosslinks. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
25(6), 1176-1182.
-
Kumar, A., & Mahapatra, R. N.
(2005).
An integrated scheduling and buffer management scheme for input queued switches with finite buffer space. Computer Communications.
29(1), 42-51.
-
Mahapatra, R. N., & Zhao, W.
(2005).
An energy-efficient slack distribution technique for multimode distributed real-time embedded systems. IEEE Transactions on Parallel and Distributed Systems.
16(7), 650-662.
-
Ravikumar, V. C., Mahapatra, R. N., & Bhuyan, L. N.
(2005).
EaseCAM: an energy and storage efficient TCAM-based router architecture for IP lookup. IEEE Transactions on Computers.
54(5), 521-533.
-
Chousein, A., & Mahapatra, R. N.
(2005).
Fully associative cache partitioning with don't care bits for real-time applications. ACM SIGBED Review.
2(2), 35-38.
-
Ravikumar, V. C., & Mahapatra, R. N.
(2004).
TCAM architecture for IP lookup using prefix properties. IEEE Micro.
24(2), 60-69.
-
Mahapatra, R. N.
(2003).
IEEE Workshop on Embedded System Codesign (ESCODES). Microelectronics Journal.
34(11), 987-987.
-
Mahapatra, S., & Mahapatra, R. N.
(2000).
Mapping of Neural Network Models onto Systolic Arrays. Journal of Parallel and Distributed Computing.
60(6), 677-689.
-
Mahapatra, S., Mahapatra, R. N., & Chatterji, B. N.
(1999).
Mapping of neural network models onto massively parallel hierarchical computer systems. Journal of Systems Architecture.
45(11), 919-929.
-
Tripathy, C. R., Mahapatra, R. N., & Misra, R. B.
(1997).
Reliability analysis of hypercube multicomputers. Microelectronics Reliability.
37(6), 885-891.
-
Das, B. K., Mahapatra, R. N., & Chatterji, B. N.
(1997).
Modelling Hadamard Haar transform algorithm for omega connected multiprocessors. Signal Processing.
58(3), 293-301.
-
Mahapatra, R. N., Kumar, A., & Chatterji, B. N.
(1997).
Performance analysis of 2-D inverse fast cosine transform employing multiprocessors. IEEE Transactions on Signal Processing.
45(5), 1323-1335.
-
Mahapatra, S., Mahapatra, R. N., & Chatterji, B. N.
(1997).
A parallel formulation of back-propagation learning on distributed memory multiprocessors. Parallel Computing.
22(12), 1661-1675.
-
Mahapatra, R. N., & Mahapatra, S.
(1996).
Mapping of neural network models onto two-dimensional processor arrays. Parallel Computing.
22(10), 1345-1357.
-
DAS, B. K., MAHAPATRA, R. N., & CHATTERJI, B. N.
(1996).
PERFORMANCE MODELING OF DISCRETE COSINE TRANSFORM FOR STAR GRAPH CONNECTED MULTIPROCESSORS. Journal of Circuits, Systems and Computers.
6(06), 635-648.
-
Tripathy, C. R., Patra, S., Misra, R. B., & Mahapatra, R. N.
(1996).
Reliability evaluation of multistage interconnection networks with multi-state elements. Microelectronics Reliability.
36(3), 423-428.
-
Mahapatra, R. N., & Mahapatra, S.
(1993).
Modelling a 2-D inverse fast cosine transform algorithm on a multistage network. Signal Processing.
30(2), 235-243.
-
Mahapatra, R. N., & Pareek, H.
(1991).
Modelling a fast parallel thinning algorithm for shared memory SIMD computers. Information Processing Letters.
40(5), 257-261.
-
DATTA, A., JOSHI, S. V., & MAHAPATRA, R. N.
(1991).
MODELLING A MORPHOLOGICAL THINNING ALGORITHM FOR SHARED MEMORY SIMD COMPUTERS. Parallel Processing Letters.
1(01), 59-65.
-
Mahapatra, R. N.
(1988).
Microprocessor Implimentation of a Fast Convolver. IETE Technical Review.
5(8), 326-328.
-
Dang, D., Chittamuru, S., Pasricha, S., Mahapatra, R., & Sahoo, D.
(2021).
BPLight-CNN: A Photonics-based Backpropagation Accelerator for Deep Learning
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book
-
Mandal, A., Khatri, S. P., & Mahapatra, R.
(2014).
Source-Synchronous Networks-On-Chip. Ed. 9781461494058.
Springer New York.
-
Kim, Y., & Mahapatra, R. N.
(2010).
Design of Low-Power Coarse-Grained Reconfigurable Architectures. Taylor & Francis.
-
Mandal, A., Khatri, S. P., & Mahapatra, R.
(2014).
Source-Synchronous Networks-On-Chip. Ed. 9781461494058.
Springer New York.
-
chapter
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2014).
Clock Distribution for Fast Networks-on-Chip. Source-Synchronous Networks-On-Chip.
(pp. 15-66).
Springer Nature.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2014).
Conclusion and Future Work. Source-Synchronous Networks-On-Chip.
(pp. 139-140).
Springer Nature.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2014).
Fast Network-on-Chip Design. Source-Synchronous Networks-On-Chip.
(pp. 67-127).
Springer Nature.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2014).
Fast On-Chip Data Transfer Using Sinusoid Signals. Source-Synchronous Networks-On-Chip.
(pp. 129-137).
Springer Nature.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2014).
Introduction. Source-Synchronous Networks-On-Chip.
(pp. 1-13).
Springer Nature.
-
Biswas, A., Mohan, S., & Mahapatra, R.
(2010).
Semantic Technologies for Distributed Search P2P Networks. Handbook of Research on P2P and Grid Systems for Service-Oriented Computing.
(pp. 88-122).
IGI Global.
-
Singhal, R., Mahapatra, R., Choi, G., & Bhojwani, P.
(2007).
Forward Error Correction For On-chip Interconnection Networks. Unique Chips and Systems.
(pp. 325-338).
Taylor & Francis.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2014).
Clock Distribution for Fast Networks-on-Chip. Source-Synchronous Networks-On-Chip.
(pp. 15-66).
Springer Nature.
-
conference paper
-
Yiu, Y. F., & Mahapatra, R.
(2020).
Heuristic Function Evolution For Pathfinding Algorithm in FPGA Accelerator. 108-115.
-
Yiu, Y. F., & Mahapatra, R.
(2020).
Multi-Agent Pathfinding with Hierarchical Evolutionary Hueristic A. 9-16.
-
Hasnain, S. A., & Mahapatra, R.
(2020).
Towards Reconfigurable Optoelectronic Hardware Accelerator for Reservoir Computing. Proceedings of SPIE.
115470w-115470w-11.
-
Dang, D., Khansama, A., Mahapatra, R., & Sahoo, D.
(2020).
BPhoton-CNN: An Ultrafast Photonic Backpropagation Accelerator for Deep Learning. 27-32.
-
Yiu, Y. F., & Mahapatra, R.
(2020).
Hierarchical Evolutionary Heuristic A* Search. 33-40.
-
Yiu, Y. F., & Mahapatra, R.
(2020).
Regions Discovery Algorithm for Pathfinding in Grid Based Maps. 84-87.
-
Hasnain, S. A., & Mahapatra, R.
(2020).
On-chip Parallel Photonic Reservoir Computing using Multiple Delay lines. Proceedings / Symposium on Computer Architecture and High Performance Computing. Symposium on Computer Architecture and High Performance Computing.
28-34.
-
Ott, K., & Mahapatra, R.
(2019).
Continuous Authentication of Embedded Software. 2019 18TH IEEE INTERNATIONAL CONFERENCE ON TRUST, SECURITY AND PRIVACY IN COMPUTING AND COMMUNICATIONS/13TH IEEE INTERNATIONAL CONFERENCE ON BIG DATA SCIENCE AND ENGINEERING (TRUSTCOM/BIGDATASE 2019).
128-135.
-
Yiu, Y. F., Du, J., & Mahapatra, R.
(2019).
Evolutionary Heuristic A* Search: Pathfinding Algorithm with Self-Designed and Optimized Heuristic Function. International Journal of Semantic Computing.
5-23.
-
Dhang, D., Hasnain, S. A., & Mahapatra, R.
(2019).
MReC: A Multilayer Photonic Reservoir Computing Architecture. Proceedings - International Symposium on Quality Electronic Design, ISQED.
170-175.
-
Dass, J., Narawane, Y., Mahapatra, R., & Sarin, V.
(2019).
FPGA-based Distributed Edge Training of SVM. 121-121.
-
Bhutra, G., Rasheed, A., & Mahapatra, R.
(2018).
Privacy-Preserving ECG based Active Authentication (PPEA2) for IoT Devices. IEEE International Performance, Computing and Communications Conference, Proceedings.
1-7.
-
Yiu, Y. F., Du, J., & Mahapatra, R.
(2018).
Evolutionary Heuristic A* search: Heuristic Function Optimization via Genetic Algorithm. 25-32.
-
Ott, K., & Mahapatra, R.
(2018).
Hardware Performance Counters for Embedded Software Anomaly Detection. 528-535.
-
Dang, D., Dass, J., & Mahapatra, R.
(2017).
ConvLight: A Convolutional Accelerator with Memristor integrated Photonic Computing. 2017 IEEE 24TH INTERNATIONAL CONFERENCE ON HIGH PERFORMANCE COMPUTING (HIPC).
114-123.
-
Rizo-Dominguez, L., Mahapatra, R., & Padilla-Cantoya, I.
(2017).
Using FPGA implementations for evaluation of Internet Retransmission-Time-Out Predictors. 1-4.
-
Dass, J., Sakuru, V., Sarin, V., & Mahapatra, R. N.
(2017).
Distributed QR decomposition framework for training Support Vector Machines. Distributed Computing Systems.
753-763.
-
Rasheed, A., Kenneth, A., Mahapatra, R., & Puthal, D.
(2017).
Private matching and set intersection computation in multi-agent and industrial control systems. 1-6.
-
Dang, D., Chittamuru, S., Mahapatra, R., & Pasricha, S.
(2017).
Islands of Heaters: A Novel Thermal Management Framework for Photonic NoCs. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
306-311.
-
Lee, K., Bhattacharya, R., Dass, J., Sakuru, V., & Mahapatra, R. N.
(2016).
A Relaxed Synchronization Approach for Solving Parallel Quadratic Programming Problems with Guaranteed Convergence. Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS.
182-191.
-
Dang, D., Patra, B., & Mahapatra, R.
(2015).
A Multilayered Design Approach for Efficient Hybrid 3D Photonics Network-on-chip. 121-126.
-
Dang, D., Patra, B., & Mahapatra, R.
(2015).
A 2-Layer Laser Multiplexed Photonic Network-on-Chip. Proceedings - International Symposium on Quality Electronic Design, ISQED.
397-401.
-
Dang, D., Patra, B., & Mahapatra, R.
(2015).
A 2-Layer Laser Multiplexed Photonic Network-on-Chip. Proceedings - International Symposium on Quality Electronic Design, ISQED.
392-396.
-
Dang, D., Mahapatra, R., & Kim, E. J.
(2015).
PID Controlled Thermal Management in Photonic Network-on-Chip. 17-23.
-
Dang, D., Patra, B., Mahapatra, R., & Fiers, M.
(2015).
Mode-Division-Multiplexed Photonic Router for High Performance Network-on-Chip. Proceedings of the IEEE International Conference on VLSI Design.
111-116.
-
Tripathy, A., Ieong, K. C., Patra, A., & Mahapatra, R.
(2013).
A Reconfigurable Computing Architecture for Semantic Information Filtering. 212-218.
-
Tripathy, A., Patra, A., Mohan, S., & Mahapatra, R.
(2013).
Distributed Collaborative Filtering on a Single Chip Cloud Computer. 140-145.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2013).
A source-synchronous Htree-based network-on-chip. 161-166.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2013).
Exploring Topologies for Source-synchronous Ring-based Network-on-Chip. Proceedings -Design, Automation and Test in Europe, DATE.
1026-1031.
-
Tripathy, A., Patra, A., Mohan, S., & Mahapatra, R.
(2012).
Designing a Collaborative Filtering Recommender on the Single Chip Cloud Computer. 838-847.
-
Tripathy, A., Mohan, S., & Mahapatra, R.
(2012).
Optimizing a Collaborative Filtering Recommender for Many-Core Processors. 261-268.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2012).
A Fast, Source-synchronous Ring-based Network-on-Chip Design. Proceedings -Design, Automation and Test in Europe, DATE.
1489-1494.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2012).
Architectural Simulations of a Fast, Source-Synchronous Ring-based Network-on-Chip Design. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
482-483.
-
Takala, J., Mahapatra, R. N., Liu, J., Xue, J., & Yang, L. T.
(2011).
Message from the Chairs. xxvii-xxviii.
-
Tripathy, A., Mohan, S., & Mahapatra, R.
(2011).
Optimizing a Semantic Comparator using CUDA-enabled Graphics Hardware. FIFTH IEEE INTERNATIONAL CONFERENCE ON SEMANTIC COMPUTING (ICSC 2011).
125-132.
-
Mohan, S., Tripathy, A., Biswas, A., & Mahapatra, R.
(2011).
Parallel Processor Core for Semantic Search Engines. 1767-1775.
-
Gupta, N., & Mahapatra, R.
(2011).
Temperature Aware Energy Management or Real-Time Scheduling. Proceedings - International Symposium on Quality Electronic Design, ISQED.
91-96.
-
Mandal, A., Jayakumar, N., Bollapalli, K., Khatri, S. P., & Mahapatra, R. N.
(2011).
An Automated Approach for Minimum Jitter Buffered H - Tree Construction. Proceedings of the IEEE International Conference on VLSI Design.
76-81.
-
Mandal, A., Karkala, V., Khatri, S. P., & Mahapatra, R. N.
(2011).
Interconnected Tile Standing Wave Resonant Oscillator based Clock Distribution Circuits. Proceedings of the IEEE International Conference on VLSI Design.
82-87.
-
Lee, J. D., Gupta, N., Mahapatra, R. N., & Manners, B. E.
(2010).
THE FAA HANDBOOK ON MICROPROCESSOR SELECTION AND EVALUATION IN AIRBORNE SYSTEMS. 5.e.4-1-5.e.4-9.
-
Mohan, S., Biswas, A., Tripathy, A., Pannigrahy, J., & Mahapatra, R.
(2010).
A Parallel Architecture for Meaning Comparison. 1-10.
-
Mandal, S. K., Denton, R., Mohanty, S. P., & Mahapatra, R. N.
(2010).
Low power nanoscale buffer management for network on chip routers. 245-250.
-
Sridharan, R., & Mahapatra, R.
(2010).
Reliability Aware Power Management for Dual-Processor Real-Time Embedded Systems. Design Automation Conference.
819-824.
-
Gupta, N., Mandal, S. K., Malave, J., Mandal, A., & Mahapatra, R. N.
(2010).
A Hardware Scheduler for Real Time Multiprocessor System on Chip. Proceedings of the IEEE International Conference on VLSI Design.
264-269.
-
Rasheed, A., & Mahapatra, R.
(2009).
Mobile Sink Using Multiple Channels to Defend Against Wormhole Attacks in Wireless Sensor Networks. IEEE International Performance, Computing and Communications Conference, Proceedings.
216-222.
-
Biswas, A., Mohan, S., Panigrahy, J., Tripathy, A., & Mahapatra, R.
(2009).
Representation of Complex Concepts for Semantic Routed Network. Lecture Notes in Computer Science.
127-138.
-
Lee, J. D., Mahapatra, R. N., & Bhojwani, P. S.
(2009).
A Distributed Concurrent On-Line Test Scheduling Protocol for Many-Core NoC-Based Systems. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
179-185.
-
Yu, H., Mahapatra, R., & Bhuyan, L.
(2009).
A Hash-based Scalable IP lookup using Bloom and Fingerprint Filters. Proceedings - International Conference on Network Protocols, ICNP.
264-+.
-
Biswas, A., Mohan, S., Tripathy, A., Panigrahy, J., & Mahapatra, R.
(2009).
Semantic Key for Meaning Based Searching. 209-214.
-
Biswas, A., Mohan, S., & Mahapatra, R.
(2009).
Search Co-ordination by Semantic Routed Network. Proceedings - International Conference on Computer Communications and Networks, ICCCN.
202-214.
-
Kim, Y., & Mahapatra, R. N.
(2009).
Dynamic Context Management for Low Power Coarse-Grained Reconfigurable Architecture. 33-38.
-
Rasheed, A., & Mahapatra, R.
(2009).
A key pre-distribution scheme for heterogeneous sensor networks. 263-268.
-
Kim, Y., & Mahapatra, R. N.
(2009).
Hierarchical Reconfigurable Computing Arrays For Efficient CGRA-based Embedded Systems. Design Automation Conference.
826-831.
-
Rasheed, A., & Mahapatra, R.
(2008).
An Efficient Key Distribution Scheme for Establishing Pairwise Keys with a Mobile Sink in Distributed Sensor Networks. IEEE International Performance, Computing and Communications Conference, Proceedings.
264-270.
-
Lee, J. D., & Mahapatra, R. N.
(2008).
In-Field NoC-Based SoC Testing with Distributed Test Vector Storage. 206-211.
-
Sridharan, R., Gupta, N., & Mahapatra, R.
(2008).
Feed back-control led reliability-aware power management for real-time embedded systems. Design Automation Conference.
185-190.
-
Mandal, S. K., Bhojwani, P. S., Mohanty, S. P., & Mahapatra, R. N.
(2008).
IntellBatt: Towards smarter battery design. Design Automation Conference.
872-877.
-
Biswas, A., Moban, S., & Mahapatra, R.
(2008).
Optimization of Semantic Routing Table. Proceedings - International Conference on Computer Communications and Networks, ICCCN.
298-303.
-
Rasheed, A., & Mahapatra, R.
(2008).
Secure Data Collection Scheme in Wireless Sensor Network with Mobile Sink. 332-340.
-
Singhal, R., Choi, G., & Mahapatra, R. N.
(2008).
Data Handling Limits of On-Chip Interconnects. IEEE Transactions on Very Large Scale Integration Systems.
707-713.
-
Dechev, D., Mahapatra, R., Stroustrup, B., & Wagner, D.
(2008).
C plus plus dynamic cast in autonomous space systems. 499-+.
-
Yu, H., & Mahapatra, R.
(2008).
A memory-efficient hashing by multi-predicate bloom filters for packet classification. IEEE Infocom. Proceedings.
2467-+.
-
Yu, H., & Mahapatra, R.
(2008).
A space- and time-efficient hash table hierarchically indexed by bloom filters. Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS.
1446-+.
-
Kim, Y., & Mahapatra, R. N.
(2008).
Reusable context pipelining for low power coarse-grained reconfigurable architecture. Proceedings of the International Parallel and Distributed Processing Symposium, IPDPS.
3379-3386.
-
Lee, J. D., Gupta, N., Bhojwani, P. S., & Mahapatra, R. N.
(2008).
An On-Demand Test Triggering Mechanism for NoC-Based Safety-Critical Systems. 184-189.
-
Mandal, S. K., & Mahapatra, R. N.
(2008).
PowerAntz: Distributed Power Sharing Strategy for Network on Chip. Proceedings of the International Symposium on Low Power Electronics and Design.
177-182.
-
Kim, Y., & Mahapatra, R. N.
(2008).
A New Array Fabric for Coarse-Grained Reconfigurable Architecture. 584-591.
-
Yu, H., & Mahapatra, R.
(2008).
A Throughput-Efficient Packet Classifier with n Bloom Filters. 1-5.
-
Samanta, R., Surprise, J., & Mahapatra, R.
(2008).
Dynamic aggregation of virtual addresses in TLB using TCAM cells. Proceedings of the IEEE International Conference on VLSI Design.
243-+.
-
Rasheed, A., & Mahapatra, R.
(2007).
An energy-efficient hybrid data collection scheme in wireless sensor networks. 703-708.
-
Leach, R. J.
(2007).
Preliminary Models of the Cost of Fault Tolerance. Proceedings / IEEE International Symposium on High-Assurance Systems Engineering. IEEE International Symposium on High-Assurance Systems Engineering.
371-372.
-
Kim, Y., & Mahapatra, R. N.
(2007).
Dynamically Compressible Context Architecture for Low Power Coarse-Grained Reconfigurable Array. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
395-400.
-
Bhojwani, P. S., & Mahapatra, R. N.
(2007).
A Robust Protocol for Concurrent On-Line Test (COLT) of NoC-based Systems-on-a-Chip. Design Automation Conference.
670-675.
-
Bhojwani, P., & Mahapatra, R. N.
(2007).
An Infrastructure Ip for Online Testing of Network-On-Chip Based Socs. 867-872.
-
Bhojwani, P. S., Lee, J. D., & Mahapatra, R. N.
(2007).
Sapp: scalable and adaptable peak power management in nocs. Proceedings of the International Symposium on Low Power Electronics and Design.
340-345.
-
Samanta, R., & Mahapatra, R. N.
(2007).
An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm. Proceedings of the IEEE International Conference on VLSI Design.
824-829.
-
Sridharan, R., & Mahapatra, R.
(2007).
Analysis.of real-time embedded applications in the presence of a stochastic fault model. Proceedings of the IEEE International Conference on VLSI Design.
83-+.
-
Nolen, J. M., & Mahapatra, R.
(2006).
A TDM test scheduling method for network-on-chip systems. Proceedings - International Workshop on Microprocessor Test and Verification.
90-+.
-
Wu, D., Hu, J., & Mahapatra, R. N.
(2006).
Antenna avoidance in layer assignment. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
734-738.
-
Singhal, R., Choi, G., & Mahapatra, R.
(2006).
Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
310-314.
-
Singhal, R., Choi, G. S., & Mahapatra, R.
(2006).
Information theoretic capacity of long on-chip interconnects in the presence of crosstalk. Proceedings - International Symposium on Quality Electronic Design, ISQED.
407-+.
-
Singhal, R., Choi, G., & Mahapatra, R. N.
(2006).
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm. Proceedings of the IEEE International Conference on VLSI Design.
1-6.
-
Bhojwani, P., & Mahapatra, R. N.
(2006).
Core Network Interface Architecture and Latency Constrained On-Chip This work was supported by NSF award, CNS-0509483. Proceedings - International Symposium on Quality Electronic Design, ISQED.
358-363.
-
Wu, D. i., Hu, J., & Mahapatra, R.
(2005).
Coupling aware timing optimization and antenna avoidance in layer assignment. 20-27.
-
Ahmad, S., & Mahapatra, R.
(2005).
TCAM enabled on-chip logic minimization. Design Automation Conference.
678-683.
-
Bhojwani, P., Mahapatra, R., Kim, E. J., & Chen, T.
(2005).
A heuristic for peak power constrained design of network-on-chip (NoC) based multimode systems. Proceedings of the IEEE International Conference on VLSI Design.
124-129.
-
Wu, D., Venkataraman, G., Hu, J., Li, Q. Y., & Mahapatra, R.
(2005).
DiCER: Distributed and cost-effective redundancy for variation tolerance. ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS.
393-397.
-
Padhi, K. P., & Mahapatra, R. N.
(2005).
Identification of Voice Segments in Stereo Soundtracks. 1566-1570.
-
Kumar, A., & Mahapatra, R. N.
(2005).
Integrated scheduling and buffer management scheme for input queued switches under extreme traffic conditions. 2013 National Conference on Communications, NCC 2013.
1020-1025.
-
Rai, V., & Mahapatra, R. N.
(2005).
Lifetime Modeling of a Sensor Network. Proceedings -Design, Automation and Test in Europe, DATE.
1-2.
-
Singhal, R., Choi, G. S., & Mahapatra, R. N.
(2005).
Quantized LDPC decoder design for binary symmetric channels. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
5782-5785.
-
Wu, D. i., Hu, J., Zhao, M., & Mahapatra, R.
(2005).
Timing driven track routing considering coupling capacitance. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
1156-1159.
-
Wu, D. i., Hu, J., Zhao, M., & Mahapatra, R.
(2005).
Timing driven track routing considering coupling capacitance. 1156-1159.
-
Ahmad, S., Jayakumar, N., Balasubramanian, V., Hursey, E., Khatri, S. P., & Mahapatra, R.
(2005).
X-routing using two Manhattan route instances. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
45-50.
-
Choudhuri, S., & Mahapatra, R. N.
(2004).
Energy characterization of filesystems for diskless embedded systems. Design Automation Conference.
566-569.
-
Rajaram, A., Hu, J., & Mahapatra, R.
(2004).
Reducing clock Skew variability via cross links. Design Automation Conference.
18-23.
-
Wu, D., Hu, J., Mahapatra, R., & Zhao, M.
(2004).
Layer assignment for crosstalk risk minimization. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
159-162.
-
Ahmad, S., & Mahapatra, R.
(2004).
m-Trie: An efficient approach to on-chip logic minimization. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
428-435.
-
Rajaram, A., Lu, B., Guo, W., Mahapatra, R., & Hu, J.
(2003).
Analytical bound for unwanted clock skew due to wire width variation. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
401-406.
-
Satpathy, M., Mahapatra, R. N., Choudhuri, S., & Chitnis, S. V.
(2003).
High Performance Code Generation through Lazy Activation Records. 37-47.
-
Bhojwani, P., & Mahapatra, R.
(2003).
Interfacing cores with on-chip packet-switched networks. Proceedings of the IEEE International Conference on VLSI Design.
382-387.
-
Ravikumar, V. C., Mahapatra, R., & Liu, J. C.
(2002).
Modified LC-Trie based efficient routing lookup. Proceedings - IEEE Computer Society's Annual International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunications Systems, MASCOTS.
177-182.
-
Pirvu, M., Bhuyan, L., & Mahapatra, R.
(2000).
Hierarchical simulation of a multiprocessor architecture. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
585-588.
-
Mahapatra, S., & Mahapatra, R. N.
(1995).
Mapping of backpropagation learning onto distributed memory multiprocessors. 217-226 vol.1-226.
-
Mahapatra, R. N., & Majumdar, J.
(1994).
Implementation of fast Hartley transform on multiple bus cache coherent multiprocessors. 96-101.
-
Mahapatra, R. N., & Kumar, A.
(1992).
Vector Hartley transform employing multiprocessors. Proceedings of the International Conference on Parallel Processing.
250-253.
-
Mahapatra, R. N., & Kar, B. K.
(1991).
A multilayered VLSI array design for multistage interconnection network. Proceedings of the IEEE International Conference on VLSI Design.
295-296.
-
Yiu, Y. F., & Mahapatra, R.
(2020).
Heuristic Function Evolution For Pathfinding Algorithm in FPGA Accelerator. 108-115.
Research
principal investigator on
Teaching
teaching activities
- CSCE312 Computer Organization Instructor
- CSCE462 Microcomputer Systems Instructor
- CSCE482 Hnr- Sr Capstone Design Instructor
- CSCE483 Computer Sys Design Instructor
- CSCE485 Directed Studies Instructor
- CSCE489 Sptp:adv Iot Instructor
- CSCE491 Hnr-research Instructor
- CSCE617 Co-design Embedded Sys Instructor
- CSCE684 Professional Internship Instructor
- CSCE684 Professional Internship: In-ab Instructor
- CSCE685 Directed Studies Instructor
- CSCE689 Sptp: Adv Iot Instructor
- CSCE691 Research Instructor
- ITDE691 Research Instructor
Works By Students
chaired theses and dissertations
-
Lee, Jason Daniel (2012-02). Concurrent Online Testing for Many Core Systems-on-Chips.
Background
education and training
- Ph.D. in Computer Engineering, Indian Institute of Technology Kharagpur - (Kharagpur, India) 1991
- M.S.E. in Electrical Engineering, Sambalpur University - (Sambalpur, Orissa, India) 1984
- B.S.E. in Electronics and Telecommunication, Sambalpur University - (Sambalpur, Orissa, India) 1979
Contact
first name
- Rabinarayan
has last name
- Mahapatra
mailing address
-
Texas A&M University
Computer Science & Engineering
3112 TAMU
College Station, TX 77843-3112
USA
Other
- rabi@tamu.edu