Implementation of fast Hartley transform on multiple bus cache coherent multiprocessors
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Hou's FHT algorithm has been considered for modeling on Multiple Bus Cache coherent multiprocessors. The analytical formulas are developed and performances are analyzed in terms of speedup using these formulas. The limitations of the inter-processor communication overhead are studied and a modification to the signal flow graph is proposed in order to minimize the multiprocessor execution time and hence improve the speedup performance of the system.
name of conference
1994 International Conference on Parallel and Distributed Systems
Proceedings of 1994 International Conference on Parallel and Distributed Systems
author list (cited authors)
Mahapatra, R. N., & Majumdar, J.
complete list of authors
Mahapatra, RN||Majumdar, J