Implementation of fast Hartley transform on multiple bus cache coherent multiprocessors Conference Paper

abstract

• Hou's FHT algorithm has been considered for modeling on Multiple Bus Cache coherent multiprocessors. The analytical formulas are developed and performances are analyzed in terms of speedup using these formulas. The limitations of the inter-processor communication overhead are studied and a modification to the signal flow graph is proposed in order to minimize the multiprocessor execution time and hence improve the speedup performance of the system.

name of conference

• Proceedings of 1994 International Conference on Parallel and Distributed Systems

authors

• Mahapatra, Rabinarayan

published proceedings

• Proceedings of 1994 International Conference on Parallel and Distributed Systems

author list (cited authors)

• Mahapatra, R. N., & Majumdar, J.

citation count

• 0

complete list of authors

• Mahapatra, RN||Majumdar, J

publication date

• January 1994

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

Digital Object Identifier (DOI)

• 10.1109/icpads.1994.590057

start page

• 96

end page

• 101

URL

• http://dx.doi.org/10.1109/icpads.1994.590057