Dynamic aggregation of virtual addresses in TLB using TCAM cells
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abstract
In this paper, we propose dynamic aggregation of virtual tags in the Translation Lookaside Buffer (TLB) to increase its storage capacity without increasing the size of the tag array. To support dynamic aggregation, we incorporate a few Ternary-CAM (TCAM) cells into the TLB tag array. The modified TLB architecture demonstrates a compression scheme that increases TLB reach with negligible overhead and no access time penalty. The performance of the proposed TLB architecture is evaluated using SPEC CPU2000 benchmarks. Simulation results indicate a significant reduction in miss ratios, nearly 100% reduction is achieved in several benchmarks, and as much as a 46% increase in IPC (Instructions per cycle) is obtained when compared to a conventional TLB with the same number of tag entries. We also evaluate the performance of our tag compressed TLB against the performance of a conventional TLB that contains an equivalent number of virtual to physical address translations. Our results show that TCAM based compression is able to achieve nearly the same system performance as the large conventional TLB while consuming on average 38% less energy and 42% less area; thus illustrating that tag compression is a more attractive solution for improving TLB performance than simply increasing the size of the TLB. 2008 IEEE.
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21st International Conference on VLSI Design (VLSID 2008)
