publication venue for
- Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage 2016
- Mode-Division-Multiplexed Photonic Router for High Performance Network-on-Chip 2015
- Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation 2014
- Sneak-path Testing of Memristor-based Memories 2013
- AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation 2011
- An Approach to Tolerate Process Related Variations in Memristor-Based Applications 2011
- An Automated Approach for Minimum Jitter Buffered H-Tree Construction 2011
- Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits 2011
- Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs 2011
- A Hardware Scheduler for Real Time Multiprocessor System on Chip 2010
- A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters 2008
- An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products 2008
- Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells 2008
- A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes 2007
- A Placement Methodology for Robust Clocking 2007
- An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm 2007
- Analysis of RealTime Embedded Applications in the Presence of a Stochastic Fault Model 2007
- Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits 2007
- Programmable LDPC decoder based on the bubble-sort algorithm 2006
- Wide Limited Switch Dynamic Logic Circuit Implementations 2006
- A heuristic for peak power constrained design of network-on-chip (NoC) based multimode systems 2005
- Non-Manhattan routing using a Manhattan router 2005
- Comparison of effectiveness of Current Ratio and Delta-I/sub DDQ/ tests 2004
- Immediate neighbor difference I/sub DDQ/ test (INDIT) for outlier identification 2003
- Interfacing cores with on-chip packet-switched networks 2003
- A multilayered VLSI array design for multistage interconnection network 1991