publication venue for
- Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage 2016
- Mode-Division-Multiplexed Photonic Router for High Performance Network-on-Chip 2015
- Techniques to Improve the Efficiency of SAT based Path Delay Test Generation 2014
- Sneak-path Testing of Memristor-based Memories 2013
- An Approach to Tolerate Process Related Variations in Memristor-Based Applications 2011
- Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs 2011
- AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation 2011
- An Automated Approach for Minimum Jitter Buffered H - Tree Construction 2011
- Interconnected Tile Standing Wave Resonant Oscillator based Clock Distribution Circuits 2011
- A Hardware Scheduler for Real Time Multiprocessor System on Chip 2010
- A merged synthesis technique for fast arithmetic blocks involving sum-of-products and shifters 2008
- An inversion-based synthesis approach for area and power efficient arithmetic sum-of-products 2008
- Dynamic aggregation of virtual addresses in TLB using TCAM cells 2008
- Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits 2007
- A parallel VLSI architecture for layered decoding for array LDPC codes 2007
- A placement methodology for robust clocking 2007
- An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm 2007
- Analysis.of real-time embedded applications in the presence of a stochastic fault model 2007
- Programmable LDPC Decoder Based on the Bubble-Sort Algorithm 2006
- A heuristic for peak power constrained design of network-on-chip (NoC) based multimode systems 2005
- Non-Manhattan routing using a Manhattan router 2005
- Wide limited switch dynamic logic circuit implementations 2005
- Comparison of effectiveness of current ratio and delta-I-DDQ tests 2004
- Immediate neighbor difference I-DDQ test (INDIT) for outlier identification 2003
- Interfacing cores with on-chip packet-switched networks 2003
- A Partition Approach to Find the Length of the Longest Common Subsequence 1993
- A multilayered VLSI array design for multistage interconnection network 1991