publication venue for
- Formal Security Verification of Third Party Intellectual Property Cores for Information Leakage 2016
- Mode-Division-Multiplexed Photonic Router for High Performance Network-on-Chip 2015
- Techniques to Improve the Efficiency of SAT based Path Delay Test Generation 2014
- Sneak-path testing of memristor-based memories 2013
- An approach to tolerate process related variations in memristor-based applications 2011
- AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation 2011
- An Automated Approach for Minimum Jitter Buffered H - Tree Construction 2011
- Interconnected Tile Standing Wave Resonant Oscillator based Clock Distribution Circuits 2011
- Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs 2011
- A Hardware Scheduler for Real Time Multiprocessor System on Chip 2010
- A Merged Synthesis Technique for Fast Arithmetic Blocks involving Sum-of-Products and Shifters 2008
- An Inversion-Based Synthesis Approach for Area and Power efficient Arithmetic Sum-of-Products 2008
- Dynamic Aggregation of Virtual Addresses in TLB using TCAM Cells 2008
- A Parallel VLSI Architecture for Layered Decoding for Array LDPC Codes 2007
- A Placement Methodology for Robust Clocking**This work was supported in part by Semiconductor Research Corporation under contract number 2004- TJ-1205. 2007
- An Enhanced CAM Architecture to Accelerate LZW Compression Algorithm 2007
- Analysis of RealTime Embedded Applications in the Presence of a Stochastic Fault Model 2007
- Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits 2007
- Programmable LDPC Decoder Based on the Bubble-Sort Algorithm 2006
- Wide Limited Switch Dynamic Logic Circuit Implementations 2006
- A Heuristic for Peak Power Constrained Design of Network-On-Chip (NoC) Based Multimode Systems 2005
- Non-Manhattan Routing using a Manhattan Router 2005
- Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests 2004
- Immediate Neighbor Difference IDDQ Test (INDIT) for Outlier Identification 2003
- Interfacing Cores with On-chip Packet-Switched Networks 2003
- A multilayered VLSI array design for multistage interconnection network 1991