Programmable LDPC decoder based on the bubble-sort algorithm Conference Paper uri icon

abstract

  • Low density parity check (LDPC) codes are one of the most powerful error correcting codes known. Recent research have pointed out their potential for a low cost, low latency hardware implementation. Due to this property, a lot of research has been done to find their suitability in different communication media. These codes have been shown to achieve near Shannon-limit performance in Wireless AWGN channels. At the same time these codes can result in significant power reduction in on-chip global and semi-global interconnects. These different applications demand a variety of LDPC coder decoder structures. This paper presents a programmable design for a parallel implementation of an LDPC decoder. The programability implies that this decoder can adapt itself to any arbitrary LDPC code for a variety of applications. This paper also presents two example configurations, with a throughput of 2.28 Gbps and 4.37 Gbps respectively. 2006 IEEE.

name of conference

  • 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)

published proceedings

  • 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design (VLSID'06)

author list (cited authors)

  • Singhal, R., Gwan Choi, .., & Mahapatra, R. N.

citation count

  • 1

complete list of authors

  • Singhal, R||Mahapatra, RN

publication date

  • January 2006

publisher