Interfacing cores with on-chip packet-switched networks
- Additional Document Info
- View All
2003 IEEE. With the emergence of the packet-switched networks as a possible system-on-chip (SoC) communication paradigm, the design of network-on-chips (NoC) has provided a challenge to the designers. Meeting latency requirements of communication among various cores is one of the crucial objectives for system designers. The core interface to the networking logic and the communication network are the key contributors to latency. With the goal of reducing this latency we examine the packetization strategies in the NoC communication. In this paper, three schemes of implementations are analyzed, and the costs in terms of latency, and area are projected through actual synthesis.
name of conference
16th International Conference on VLSI Design. Concurrently with the 2nd International Conference on Embedded Systems Design
16th International Conference on VLSI Design, 2003. Proceedings.
author list (cited authors)
Bhojwani, P., & Mahapatra, R.
complete list of authors
Bhojwani, P||Mahapatra, R