Interfacing cores with on-chip packet-switched networks Conference Paper

abstract

• 2003 IEEE. With the emergence of the packet-switched networks as a possible system-on-chip (SoC) communication paradigm, the design of network-on-chips (NoC) has provided a challenge to the designers. Meeting latency requirements of communication among various cores is one of the crucial objectives for system designers. The core interface to the networking logic and the communication network are the key contributors to latency. With the goal of reducing this latency we examine the packetization strategies in the NoC communication. In this paper, three schemes of implementations are analyzed, and the costs in terms of latency, and area are projected through actual synthesis.

name of conference

• 16th International Conference on VLSI Design, 2003. Proceedings.

authors

• Mahapatra, Rabinarayan

published proceedings

• 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS

author list (cited authors)

• Bhojwani, P., & Mahapatra, R.

citation count

• 30

complete list of authors

• Bhojwani, P||Mahapatra, R

publication date

• January 2003

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings of the IEEE International Conference on VLSI Design  Journal

keywords

• 33 Built Environment And Design
• 3301 Architecture
• 3303 Design
• 40 Engineering
• 4008 Electrical Engineering
• 4009 Electronics, Sensors And Digital Hardware

Digital Object Identifier (DOI)

• 10.1109/ICVD.2003.1183166

International Standard Book Number (ISBN) 10

• 0-7695-1868-0

start page

• 382

end page

• 387

volume

• 2003-January

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ficvd.2003.1183166