Interconnected Tile Standing Wave Resonant Oscillator based Clock Distribution Circuits Conference Paper uri icon


  • Standing wave oscillators (SWOs) are attractive since they can sustain extremely high oscillation frequencies with very low power consumption due to their resonant nature. In this paper, we present a technique to design a high frequency SWO to cover a large area on an IC. We achieve this by combining two techniques. The first technique increases the area coverage of an individual SWO by ensuring that it sustains an odd number (greater than one) of standing waves along the ring. The second approach further increases the area coverage by tiling multiple SWOs side by side, and connecting them such that they oscillate with the same high frequency and phase. The combined approach is simulated for a 3x3 array of tiles, using 3D, skin-effect adjusted RLC parasitic extraction. Our simulations are performed using a 90nm process, and indicate that this tiled structure can oscillate at about 7.25 GHz, with low power (about 68 mW per SWO tile) and low jitter (about 3.1% of the nominal clock period). 2011 IEEE.

name of conference

  • 2011 24th Internatioal Conference on VLSI Design

published proceedings

  • 2011 24th Internatioal Conference on VLSI Design

author list (cited authors)

  • Mandal, A., Karkala, V., Khatri, S. P., & Mahapatra, R. N.

citation count

  • 7

complete list of authors

  • Mandal, Ayan||Karkala, Vinay||Khatri, Sunil P||Mahapatra, Rabi N

publication date

  • January 2011