Savari, S. A., Yazdi, S., Abedini, N., & Khatri, S. P.
(2012).On Optimal and Achievable Fix-Free Codes. IEEE TRANSACTIONS ON INFORMATION THEORY.
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Bollapalli, K. C., Khatri, S. P., & Kish, L. B.
(2011).Digital Logic Using Non-DC Signals. Gulati, K. (Eds.),
ADVANCED TECHNIQUES IN LOGIC SYNTHESIS, OPTIMIZATIONS AND APPLICATIONS.
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Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Bus Expansion Encoder. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
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Springer US.
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Bus Stuttering Encoder. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 189-199).
Springer US.
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).Computing Leakage Current Distributions. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 15-31).
Springer US.
Garg, R., & Khatri, S. P.
(2010).Conclusions and Future Directions. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 189-193).
Springer US.
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).Design of the Chip. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 163-175).
Springer US.
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).Existing Leakage Minimization Approaches. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
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Springer US.
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).Experimental Results. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 193-199).
Springer US.
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).Exploiting Leakage: Sub-threshold Circuit Design. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 109-114).
Springer US.
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Future Trends and Applications. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 219-226).
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Gulati, K., & Khatri, S. P.
(2010).Hardware Platforms. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
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Springer US.
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Impedance Compensation. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 201-218).
Springer US.
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).Implementation of the Chip. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 177-191).
Springer US.
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Introduction to Off-Chip Crosstalk. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 107-124).
Springer US.
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Memory-based Crosstalk Avoidance Codes. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
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Springer US.
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Memoryless Crosstalk Avoidance Codes. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 27-45).
Springer US.
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).Optimum VDD for Minimum Energy. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 129-142).
Springer US.
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Preliminaries and Terminology. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 137-144).
Springer US.
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Preliminaries to On-Chip Crosstalk. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 13-26).
Springer US.
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Summary of Off-Chip Crosstalk Avoidance. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
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Springer US.
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).Summary of On-Chip Crosstalk Avoidance. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
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Springer US.
Douglass, A. J., & Khatri, S. P.
(2017).Fast, Ring-based Design of 3D Stacked DRAM. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
665-672.
Abusultan, M., & Khatri, S. P.
(2016).A Flash-based Digital Circuit Design Flow. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
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Lin, P., & Khatri, S. P.
(2010).Inference of Gene Predictor Set Using Boolean Satisfiability. IEEE International Workshop on Genomic Signal Processing and Statistics : [proceedings]. IEEE International Workshop on Genomic Signal Processing and Statistics.
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Croix, J. F., & Khatri, S. P.
(2009).Introduction to GPU programming for EDA. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
276-280.
Duperre, J., Burgett, G., Gargi, R., & Khatri, S. P.
(2009).RF Receiver and Transmitter for Insect Mounted Sensor Platform. The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS. Midwest Symposium on Circuits and Systems.
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Dash, R., Garg, R., Khatri, S. P., & Choi, G.
(2009).SEU Hardened Clock Regeneration Circuits. Proceedings - International Symposium on Quality Electronic Design, ISQED.
806-813.
Das, S., & Khatri, S. P.
(2007).Timing-Driven Decomposition of a Fast Barrel Shifter. The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS. Midwest Symposium on Circuits and Systems.
574-577.
Kim, E., Jayakumar, N., Bhagwat, P., Selvarathinam, A., Choi, G., & Khatri, S. P.
(2006).A high-speed fully-programmable VLSI decoder for regular LDPC codes. Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference).
3423-3426.
Duan, C., Gulati, K., & Khatri, S. P.
(2006).Memory-based cross-talk canceling CODECs for on-chip buses. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
1119-1122.
Jayakumar, N., Khatri, S., Gulati, K., & Sprintson, A.
(2006).Network Coding for Routability Improvement in VLSI. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
820-823.
Gulati, K., Lovell, M., & Khatri, S. P.
(2006).Efficient don't care computation for hierarchical designs. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
3037-3040.
Ahmad, S., Jayakumar, N., Balasubramanian, V., Hursey, E., Khatri, S. P., & Mahapatra, R.
(2005).X-routing using two Manhattan route instances. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
45-50.