HR job title
- Professor
- Contact Info
- 1 979 845 8371
Khatri, Sunil Professor
Positions
My research areas include Computer-aided design of Very Large Scale Integration (VLSI) ICs, including logic and physical design automation.
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Overview
Publications
selected publications
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academic article
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Fairouz, A. A., Abusultan, M., Fedorov, V. V., & Khatri, S. P.
(2021).
Hardware Acceleration of Hash Operations in Modern Microprocessors. IEEE Transactions on Computers.
70(9), 1412-1426.
-
King, J. W., Shah, M. D., Marianno, C. M., Khatri, S. P., & Chirayath, S. S.
(2021).
Computational evaluation of a novel beta radiation probe design using integrated circuits. SN Applied Sciences.
3(3), 386.
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Douglass, A. J., & Khatri, S. P.
(2019).
Fast, Ring-Based Design of 3-D Stacked DRAM. 27(8), 1731-1741.
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Kawam, A. A., Khatri, S., & Datta, A.
(2018).
A GPU-CPU heterogeneous algorithm for NGS read alignment. International Journal of Computational Biology and Drug Design.
11(1/2), 52-52.
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Al Kawam, A., Khatri, S., & Datta, A.
(2017).
A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing. 14(6), 1202-1213.
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Shah, M. D., Marianno, C., Khatri, S. P., & Fisher, B. D.
(2017).
A Neutron Detector Using Integrated Circuits. 1(1), 3-7.
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Fedorov, V. V., Abusultan, M., & Khatri, S. P.
(2016).
FTCAM: An Area-Efficient Flash-Based Ternary CAM Design. IEEE Transactions on Computers.
65(8), 2652-2658.
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Kish, L. B., Granqvist, C., Khatri, S. P., & Peper, F.
(2016).
Response to "Comment on 'Zero and negative energy dissipation at information-theoretic erasure'". Journal of Computational Electronics.
15(1), 343-346.
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Kish, L. B., Granqvist, C., Khatri, S. P., & Peper, F.
(2016).
Zero and negative energy dissipation at information-theoretic erasure. Journal of Computational Electronics.
15(1), 335-339.
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Hearn, G., Marianno, C., Khatri, S., & Grypp, M.
(2014).
List mode with the ORTEC digiBASE-E. Health Physics: the radiation safety journal.
106(2 Suppl 1), S12-S15.
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Croix, J. F., Gulati, K., & Khatri, S. P.
(2013).
Using GPUs to Accelerate CAD Algorithms. IEEE Design and Test.
30(1), 8-16.
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Savari, S. A., Yazdi, S., Abedini, N., & Khatri, S. P.
(2012).
On Optimal and Achievable Fix-Free Codes. IEEE TRANSACTIONS ON INFORMATION THEORY.
58(8), 5112-5129.
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Kish, L. B., Khatri, S. P., Bezrukov, S. M., Peper, F., Gingl, Z., & Horvath, T.
(2011).
Noise-based Deterministic Logic and Computing: a Brief Survey. INTERNATIONAL JOURNAL OF UNCONVENTIONAL COMPUTING.
7(1-2), 101-113.
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Turker, D. Z., Khatri, S. P., & Sanchez-Sinencio, E.
(2011).
A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications. IEEE Transactions on Circuits and Systems Part 1: Regular Papers.
58(6), 1225-1238.
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Kish, L. B., Khatri, S., & Horvath, T.
(2011).
Computation using noise-based logic: efficient string verification over a slow communication channel. European Physical Journal B: Condensed Matter and Complex Systems.
79(1), 85-90.
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Kish, L. B., Khatri, S., & Peper, F.
(2010).
INSTANTANEOUS NOISE-BASED LOGIC. Fluctuation and Noise Letters (FNL).
9(4), 323-330.
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Gingl, Z., Kish, L. B., & Khatri, S. P.
(2010).
TOWARDS BRAIN-INSPIRED COMPUTING. Fluctuation and Noise Letters (FNL).
9(4), 403-412.
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Jayakumar, N., & Khatri, S. P.
(2010).
A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty. ACM Transactions on Design Automation of Electronic Systems.
16(1), 9-20.
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Ekambavanan, S., Garg, R., Khatri, S. P., & Narayanan, K. R.
(2009).
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. Journal of Low Power Electronics.
5(2), 157-172.
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Bollapalli, K. C., Garg, R., Gulati, K., & Khatri, S. P.
(2009).
Selective Forward Body Bias for High Speed and Low Power SRAMs. Journal of Low Power Electronics.
5(2), 185-195.
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Garg, R., Jayakumar, N., Khatri, S. P., & Choi, G. S.
(2009).
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. 17(6), 781-792.
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Kish, L. B., Khatri, S., & Sethuraman, S.
(2009).
Noise-based logic hyperspace with the superposition of 2(N) states in a single wire. Physics Letters A: General Physics, Nonlinear Science, Statistical Physics, Atomic, Molecular and Cluster Physics, Plasma and Fluid Physics, Condensed Matter, Cross-disciplinary Physics, Biological Physics, Nanosciences, Quantum Physics.
373(22), 1928-1934.
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Duan, C., Calle, V., & Khatri, S. P.
(2009).
Efficient On-Chip Crosstalk Avoidance CODEC Design. IEEE Transactions on Very Large Scale Integration Systems.
17(4), 551-560.
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Gulati, K., Paul, S., Khatri, S. P., Patil, S., & Jas, A.
(2009).
FPGA-Based Hardware Acceleration for Boolean Satisfiability. ACM Transactions on Design Automation of Electronic Systems.
14(2), 33-11.
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Paul, S., Jayakumar, N., & Khatri, S. P.
(2009).
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations. IEEE Transactions on Very Large Scale Integration Systems.
17(2), 269-277.
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Kapoor, A., Jayakumar, N., & Khatri, S. P.
(2008).
Dynamically de-skewable clock distribution methodology. IEEE Transactions on Very Large Scale Integration Systems.
16(9), 1220-1229.
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Gulati, K., Waghmode, M., Khatri, S. P., & Shi, W.
(2008).
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. IET Computers and Digital Techniques.
2(3), 214-229.
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Das, S., & Khatri, S. P.
(2008).
Resource sharing among mutually exclusive sum-of-product blocks for area reduction. ACM Transactions on Design Automation of Electronic Systems.
13(3), 51-7.
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Gulati, K., Jayakumar, N., Khatri, S. P., & Walker, D.
(2008).
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration.
41(3), 399-412.
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Saluja, N., Gulati, K., & Khatri, S. P.
(2008).
SAT-based ATPG using multilevel compatible don't-cares. ACM Transactions on Design Automation of Electronic Systems.
13(2), 24-18.
-
Das, S., & Khatri, S. P.
(2008).
A novel hybrid parallel-prefix adder architecture with efficient timing-area characteristic. IEEE Transactions on Very Large Scale Integration Systems.
16(3), 326-331.
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Das, S., & Khatri, S. P.
(2008).
A timing-driven approach to synthesize fast barrel shifters. IEEE Transactions on Circuits and Systems, Part 2: Express Briefs.
55(1), 31-35.
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Lee, H., Cooper, R., Mika, B., Clayton, D., Garg, R., Gonzalez, J. M., ... Liang, H.
(2007).
Polymeric Sensors to Monitor Cockroach Locomotion. IEEE Sensors Journal.
7(12), 1698-1702.
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Nagarajan, V., Laendner, S., Milenkovic, O., Jayakumar, N., & Khatri, S. P.
(2007).
High-throughput VLSI implementations of iterative decoders and related code construction problems. Journal of Signal Processing Systems.
49(1), 185-206.
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Jayakumar, N., & Khatri, S. P.
(2007).
A predictably low-leakage ASIC design style. IEEE Transactions on Very Large Scale Integration Systems.
15(3), 276-285.
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Khatri, S. P., Sinha, S., Brayton, R. K., & Sangiovanni-Vincentelli, A. L.
(2004).
SPFD-based wire removal in standard-cell and network-of-PLA circuits. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
23(7), 1020-1030.
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Das, S., & Khatri, S. P.
(2002).
An Efficient and Regular Routing Methodology for Datapath Designs Using Net Regularity Extraction. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
21(1), 93-101.
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Khatri, S. P., Mehrotra, A., Brayton, R. K., Otten, R., & Sangiovanni-Vincentelli, A.
(1999).
Novel VLSI layout fabric for deep sub-micron applications. Design Automation Conference.
491-496.
-
Fairouz, A. A., Abusultan, M., Fedorov, V. V., & Khatri, S. P.
(2021).
Hardware Acceleration of Hash Operations in Modern Microprocessors. IEEE Transactions on Computers.
70(9), 1412-1426.
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book
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Mandal, A., Khatri, S. P., & Mahapatra, R.
(2014).
Source-Synchronous Networks-On-Chip. Ed. 9781461494058.
Springer New York.
-
Lin, P., & Khatri, S. P.
(2014).
Logic Synthesis for Genetic Diseases, Modeling Disease Behavior Using Boolean Networks. Ed. 9781461494294.
Springer Nature.
-
Khatri, S. P., & Gulati, K.
(2011).
Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York.
-
Khatri, S. P., & Gulati, K.
(2011).
Introduction. Springer New York.
-
Garg, R., & Khatri, S. P.
(2010).
Analysis and Design of Resilient VLSI Circuits, Mitigating Soft Errors and Process Variations. Springer Nature.
-
Gulati, K., & Khatri, S. P.
(2010).
Hardware Acceleration of EDA Algorithms, Custom ICs, FPGAs and GPUs. Springer Nature.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Minimizing and Exploiting Leakage in VLSI Design. Springer Nature.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
On and Off-Chip Crosstalk Avoidance in VLSI Design. Springer Nature.
-
Mandal, A., Khatri, S. P., & Mahapatra, R.
(2014).
Source-Synchronous Networks-On-Chip. Ed. 9781461494058.
Springer New York.
-
chapter
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Khatri, S. P., Shenoy, N. V., Giomi, J. C., & Khouja, A.
(2017).
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology. Lavagno, L., Markov, I. L., Martin, G., & Scheffer, L. K. (Eds.),
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology.
(pp. 27-56).
CRC Press.
-
Cobb, J. L., Gulati, K., & Khatri, S. P.
(2011).
A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations. ADVANCED TECHNIQUES IN LOGIC SYNTHESIS, OPTIMIZATIONS AND APPLICATIONS.
(pp. 309-334).
Springer Nature.
-
Bollapalli, K. C., Khatri, S. P., & Kish, L. B.
(2011).
Digital Logic Using Non-DC Signals. Gulati, K. (Eds.),
ADVANCED TECHNIQUES IN LOGIC SYNTHESIS, OPTIMIZATIONS AND APPLICATIONS.
(pp. 383-400).
Springer Nature.
-
Khatri, S. P., & Gulati, K.
(2011).
Advanced Techniques in Logic Synthesis, Optimizations and Applications Introduction. ADVANCED TECHNIQUES IN LOGIC SYNTHESIS, OPTIMIZATIONS AND APPLICATIONS.
(pp. 1-6).
-
Garg, R., & Khatri, S. P.
(2010).
3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuits. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 71-86).
Springer US.
-
Garg, R., & Khatri, S. P.
(2010).
A Variation Tolerant Combinational Circuit Design Approach Using Parallel Gates. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 153-171).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Accelerating Boolean Satisfiability on a Custom IC. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 33-61).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Accelerating Boolean Satisfiability on a Graphics Processing Unit. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 83-99).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Accelerating Boolean Satisfiability on an FPGA. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 63-81).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Accelerating Circuit Simulation Using Graphics Processors. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 153-165).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Accelerating Fault Simulation Using Graphics Processors. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 119-132).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Accelerating Statistical Static Timing Analysis Using Graphics Processors. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 105-118).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Adaptive Body Biasing to Compensate for PVT Variations. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 115-128).
Springer US.
-
Garg, R., & Khatri, S. P.
(2010).
Analysis and Design of Resilient VLSI Circuits Mitigating Soft Errors and Process Variations Introduction. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 1-17).
Springer US.
-
Garg, R., & Khatri, S. P.
(2010).
Analytical Determination of Radiation-induced Pulse Width in Combinational Circuits. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 21-40).
Springer US.
-
Garg, R., & Khatri, S. P.
(2010).
Analytical Determination of the Radiation-induced Pulse Shape. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 41-58).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Analytical Model for Off-Chip Bus Performance. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 145-160).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Automated Approach for Graphics Processor Based Software Acceleration. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 169-180).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Bus Expansion Encoder. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 167-187).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Bus Stuttering Encoder. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 189-199).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
CODEC Designs for Memoryless Crosstalk Avoidance Codes. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 47-72).
Springer US.
-
Garg, R., & Khatri, S. P.
(2010).
Clamping Diode-based Radiation Tolerant Circuit Design Approach. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 87-108).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Computing Leakage Current Distributions. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 15-31).
Springer US.
-
Garg, R., & Khatri, S. P.
(2010).
Conclusions and Future Directions. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 189-193).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Design of the Chip. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 163-175).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Existing Leakage Minimization Approaches. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 9-14).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Experimental Results. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 193-199).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Exploiting Leakage: Sub-threshold Circuit Design. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 109-114).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Fault Table Generation Using Graphics Processors. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 133-152).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Finding a Minimal Leakage Vector in the Presence of Random PVT Variations Using Signal Probabilities. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 33-54).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Future Trends and Applications. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 219-226).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
GPU Architecture and the CUDA Programming Model. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 23-30).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Hardware Acceleration of EDA Algorithms Custom ICs, FPGAs and GPUs Conclusions. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 181-187).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Hardware Acceleration of EDA Algorithms Custom ICs, FPGAs and GPUs Introduction. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 1-5).
Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Hardware Platforms. HARDWARE ACCELERATION OF EDA ALGORITHMS: CUSTOM ICS, FPGAS AND GPUS.
(pp. 9-22).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Impedance Compensation. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 201-218).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Implementation of the Chip. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 177-191).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Introduction of On-Chip Crosstalk Avoidance. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 3-+).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Introduction to Off-Chip Crosstalk. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 107-124).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Leakage Reduction Techniques: Minimizing Leakage in Modern Day DSM Processes Conclusions and Future Directions. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 101-105).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Memory-based Crosstalk Avoidance Codes. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 73-86).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Memoryless Crosstalk Avoidance Codes. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 27-45).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Minimizing and Exploiting Leakage in VLSI Design Introduction. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 1-6).
Springer US.
-
Garg, R., & Khatri, S. P.
(2010).
Modeling Dynamic Stability of SRAMs in the Presence of Radiation Particle Strikes. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 59-70).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Multi-Valued Logic Crosstalk Avoidance Codes. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 87-99).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Optimal Bus Sizing. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 161-166).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Optimum Reverse Body Biasing for Leakage Minimization. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 91-100).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Optimum VDD for Minimum Energy. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 129-142).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Package Construction and Electrical Modeling. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 125-136).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Practical Methodologies for Sub-threshold Circuit Design: Exploiting Leakage Through Sub-threshold Circuit Design Conclusions and Future Directions. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 157-159).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Preliminaries and Terminology. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 137-144).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Preliminaries to On-Chip Crosstalk. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 13-26).
Springer US.
-
Garg, R., & Khatri, S. P.
(2010).
Process Variation Tolerant Single-supply True Voltage Level Shifter. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 173-188).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Reclaiming the Sub-threshold Speed Penalty Through Micropipelining. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 143-155).
Springer US.
-
Garg, R., & Khatri, S. P.
(2010).
Sensitizable Statistical Timing Analysis. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 131-151).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Simultaneous Input Vector Control and Circuit Modification. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 77-90).
Springer US.
-
Garg, R., & Khatri, S. P.
(2010).
Split-output-based Radiation Tolerant Circuit Design Approach. ANALYSIS AND DESIGN OF RESILIENT VLSI CIRCUITS.
(pp. 109-127).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Summary of Off-Chip Crosstalk Avoidance. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 227-229).
Springer US.
-
Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
Summary of On-Chip Crosstalk Avoidance. ON AND OFF-CHIP CROSSTALK AVOIDANCE IN VLSI DESIGN.
(pp. 101-103).
Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
The HL Approach: A Low-Leakage ASIC Design Methodology. MINIMIZING AND EXPLOITING LEAKAGE IN VLSI DESIGN.
(pp. 55-76).
Springer US.
-
Khatri, S. P., & Shenoy, N. V.
(2006).
Logic synthesis. EDA for IC Implementation, Circuit Design, and Process Technology.
2-1-2-26.
-
Khatri, S. P., Shenoy, N. V., Giomi, J. C., & Khouja, A.
(2017).
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology. Lavagno, L., Markov, I. L., Martin, G., & Scheffer, L. K. (Eds.),
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology.
(pp. 27-56).
CRC Press.
-
conference paper
-
Scott, K. R., & Khatri, S. P.
(2022).
A Flash-based Digital to Analog Converter for Low Power Applications. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
1-8.
-
Saleh, M. A., Refaat, S. S., Khatri, S. P., & Ghrayeb, A.
(2022).
Detection and Classification of Defects in XLPE Power Cable Insulation via Machine Learning Algorithms. 1-6.
-
Scott, K. R., Khatri, S. P., & Ghrayeb, A.
(2022).
Formal Verification of a Dynamic Multi-factor Secure Communication Protocol. 1-6.
-
Scott, K. R., Lee, C., Khatri, S. P., & Vrudhula, S.
(2022).
A Flash-based Current-mode IC to Realize Quantized Neural Networks. Proceedings -Design, Automation and Test in Europe, DATE.
1029-1034.
-
Lee, C., Bharathi, K., Lansford, J., & Khatri, S. P.
(2021).
NIST-Lite: Randomness Testing of RNGs on an Energy-Constrained Platform. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
41-48.
-
Bharathi, K., Hu, J., & Khatri, S. P.
(2020).
Scaled Population Subtraction for Approximate Computing. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
348-355.
-
Zhou, H. e., Khatri, S. P., Hu, J., & Liu, F.
(2019).
A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation. Design Automation Conference.
1-6.
-
Bharathi, K., Kumar, H., Fairouz, A., Al Kawam, A., & Khatri, S. P.
(2018).
A Plain-text Incremental Compression (PIC) Technique with Fast Lookup Ability. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
389-396.
-
Douglass, A. J., & Khatri, S. P.
(2018).
Synchronization of Ring-based Resonant Standing Wave Oscillators for 3D Clocking Applications. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
318-325.
-
Fairouz, A., Abusultan, M., Elshennawy, A., & Khatri, S. P.
(2018).
Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router. Journal of Low Power Electronics.
414-427.
-
Loyka, K., Zhou, H. e., & Khatri, S. P.
(2018).
A Homomorphic Encryption Scheme Based on Affine Transforms. Proceedings of the IEEE Great Lakes Symposium on VLSI.
51-56.
-
Fairouz, A., & Khatri, S. P.
(2017).
An FPGA-based Coprocessor for Hash Unit Acceleration. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
301-304.
-
Douglass, A. J., & Khatri, S. P.
(2017).
Fast, Ring-based Design of 3D Stacked DRAM. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
665-672.
-
Zhou, H. e., Khatri, S. P., Hu, J., Liu, F., & Sze, C.
(2017).
Fast and Highly Scalable Bayesian MDP on a GPU Platform. 158-167.
-
Sharma, K., & Khatri, S.
(2017).
A Robust C-element Design with Enhanced Metastability Performance. 95-100.
-
Fairouz, A., Abusultan, M., & Khatri, S. P.
(2017).
Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors. 101-106.
-
Abusultan, M., & Khatri, S. P.
(2017).
Design of a Flash-based Circuit for Multi-valued Logic. 41-46.
-
Abusultan, M., & Khatri, S. P.
(2016).
A Flash-based Digital Circuit Design Flow. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
1-6.
-
Fairouz, A., Abusultan, M., & Khatri, S. P.
(2016).
A Novel Hardware Hash Unit Design for Modern Microprocessors. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
412-415.
-
Kottapalli, V., & Khatri, S.
(2016).
A practical methodology to validate the statistical behavior of bloom filters. 1-8.
-
Abusultan, M., & Khatri, S. P.
(2016).
Exploring Static and Dynamic Flash-based FPGA Design Topologies. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
416-419.
-
Abusultan, M., & Khatri, S. P.
(2016).
Implementing Low Power Digital Circuits using Flash Devices. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
109-116.
-
Abusultan, M., Chakravorty, S., & Khatri, S. P.
(2016).
A GPU-based Implementation of a Sensor Tasking Methodology. 1398-1405.
-
Abusultan, M., & Khatri, S. P.
(2016).
A Ternary-valued, Floating Gate Transistor-based Circuit Design Approach. Proceedings of IEEE Computer Society Annual Symposium on VLSI, ISVLSI.
719-724.
-
Zhou, H. e., Hu, J., Khatri, S. P., Liu, F., Sze, C., & Yousefi, M. R.
(2016).
GPU Acceleration for Bayesian Control of Markovian Genetic Regulatory Networks. 304-307.
-
de Aguiar, J. M., & Khatri, S. P.
(2015).
Exploring the Viability of Stochastic Computing. 391-394.
-
Kish, L. B., Granqvist, C. G., Khatri, S. P., & Smulko, J. M.
(2015).
Critical Remarks on Landauer's principle of erasure-dissipation Including notes on Maxwell demons and Szilard engines. 1-4.
-
Murray, L., & Khatri, S. P.
(2015).
An Efficient Approach to Sample On-Chip Power Supplies. 241-244.
-
Abusultan, M., & Khatri, S. P.
(2015).
Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs. 111-114.
-
Fedorov, V. V., Abusultan, M., & Khatri, S. P.
(2014).
An Area-efficient Ternary CAM Design using Floating Gate Transistors. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
55-60.
-
Elshennawy, A., & Khatri, S. P.
(2014).
An Asynchronous Network-on-Chip Router with Low Standby Power. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
394-399.
-
Abusultan, M., & Khatri, S. P.
(2014).
Look-up Table Design for Deep Sub-threshold through Full-supply Operation. 259-266.
-
Abusultan, M., & Khatri, S. P.
(2014).
A Comparison of FinFET based FPGA LUT Designs. Proceedings of the IEEE Great Lakes Symposium on VLSI.
353-358.
-
Bian, K., Walker, D., & Khatri, S. P.
(2014).
Techniques to Improve the Efficiency of SAT based Path Delay Test Generation. Proceedings of the IEEE International Conference on VLSI Design.
50-55.
-
Mandal, A., Bollapalli, K. C., Jayakumar, N., Khatri, S. P., & Mahaptra, R. N.
(2013).
A Low-jitter Phase-locked Resonant Clock Generation and Distribution Scheme. 487-490.
-
Kumar, R., & Khatri, S. P.
(2013).
Crosstalk Avoidance Codes for 3D VLSI. Proceedings -Design, Automation and Test in Europe, DATE.
1673-1678.
-
Bian, K., Walker, D., Khatri, S. P., & Lahiri, S.
(2013).
Mixed Structural-Functional Path Delay Test Generation and Compaction. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
7-12.
-
Lin, P., & Khatri, S. P.
(2013).
Noise-based Algorithms for Functional Equivalence and Tautology Checking. 235-240.
-
Elshennawy, A., Marianno, C. M., & Khatri, S. P.
(2013).
Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector. 329-330.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2013).
A source-synchronous Htree-based network-on-chip. 161-166.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2013).
Exploring Topologies for Source-synchronous Ring-based Network-on-Chip. Proceedings -Design, Automation and Test in Europe, DATE.
1026-1031.
-
Belsare, A., Liu, S., & Khatri, S.
(2013).
GPU implementation of a scalable non-linear congruential generator for cryptography applications. 89-94.
-
Lin, P., & Khatri, S. P.
(2012).
Determining Gene Function in Boolean Networks using Boolean Satisfiability. IEEE International Workshop on Genomic Signal Processing and Statistics : [proceedings]. IEEE International Workshop on Genomic Signal Processing and Statistics.
176-179.
-
Kumar, R., Mandal, A., & Khatri, S. P.
(2012).
An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
195-200.
-
Swaminathan, S. P., Lin, P., & Khatri, S. P.
(2012).
Timing Aware Partitioning for Multi-FPGA Based Logic Simulation Using Top-down Selective Hierarchy Flattening. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
153-158.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2012).
A Fast, Source-synchronous Ring-based Network-on-Chip Design. Proceedings -Design, Automation and Test in Europe, DATE.
1489-1494.
-
Bhadviya, B., Mandal, A., & Khatri, S. P.
(2012).
Alleviating NBTI-induced failure in off-chip output drivers. 295-298.
-
Lin, P., & Khatri, S. P.
(2012).
Application of Logic Synthesis to the Understanding and Cure of Genetic Diseases. Design Automation Conference.
734-740.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2012).
Architectural Simulations of a Fast, Source-Synchronous Ring-based Network-on-Chip Design. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
482-483.
-
Lin, P., Mandal, A., & Khatri, S. P.
(2012).
Boolean Satisfiability using Noise Based Logic. Design Automation Conference.
1256-1257.
-
Lin, P., Mandal, A., & Khatri, S. P.
(2012).
Boolean satisfiability using noise based logic. Design Automation Conference.
1256-1257.
-
Lin, P., & Khatri, S. P.
(2012).
Application of Max-SAT-based ATPG to optimal cancer therapy design. BMC GENOMICS.
S5-S5.
-
Lin, P., & Khatri, S. P.
(2011).
Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG. IEEE International Workshop on Genomic Signal Processing and Statistics : [proceedings]. IEEE International Workshop on Genomic Signal Processing and Statistics.
87-90.
-
Lin, P., Ivanov, A., Johnson, B., & Khatri, S. P.
(2011).
A Novel Cryptographic Key Exchange Scheme using Resistors. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
451-452.
-
Kish, L. B., Khatri, S. P., Bezrukov, S. M., Peper, F., Gingl, Z., & Horvath, T.
(2011).
Noise-based Information Processing Noise-based logic and computing: what do we have so far?. 28-33.
-
Mandal, A., Jayakumar, N., Bollapalli, K., Khatri, S. P., & Mahapatra, R. N.
(2011).
An Automated Approach for Minimum Jitter Buffered H - Tree Construction. Proceedings of the IEEE International Conference on VLSI Design.
76-81.
-
Mandal, A., Karkala, V., Khatri, S. P., & Mahapatra, R. N.
(2011).
Interconnected Tile Standing Wave Resonant Oscillator based Clock Distribution Circuits. Proceedings of the IEEE International Conference on VLSI Design.
82-87.
-
Karkala, V., Wanstrath, J., Lacour, T., & Khatri, S. P.
(2010).
Efficient Arithmetic Sum-of-Product (SOP) based Multiple Constant Multiplication (MCM) for FFT. ICCAD / IEEE/ACM International Conference on Computer-Aided Design. IEEE/ACM International Conference on Computer-Aided Design.
735-738.
-
Lin, P., & Khatri, S. P.
(2010).
Inference of Gene Predictor Set Using Boolean Satisfiability. IEEE International Workshop on Genomic Signal Processing and Statistics : [proceedings]. IEEE International Workshop on Genomic Signal Processing and Statistics.
1-4.
-
Gope, D., Lin, P., & Khatri, S. P.
(2010).
Exploring a Circuit Design Approach based on One-hot Multi-valued Domino Logic. The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS. Midwest Symposium on Circuits and Systems.
69-72.
-
Gulati, K., & Khatri, S. P.
(2010).
Fault Table Computation on GPUs. Journal of Electronic Testing.
195-209.
-
Bollapalli, K. C., Khatri, S. P., & Kish, L. B.
(2010).
Implementing Digital Logic with Sinusoidal Supplies. Proceedings -Design, Automation and Test in Europe, DATE.
315-318.
-
Kumar, R., & Khatri, S. P.
(2010).
An efficient pulse flip-flop based launch-on-shift scan cell. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
4105-4108.
-
Gulati, K., & Khatri, S. P.
(2010).
Boolean satisfiability on a graphics processor. 123-126.
-
Lin, P., & Khatri, S. P.
(2010).
VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. 381-384.
-
Abedini, N., Khatri, S. P., & Savari, S. A.
(2010).
A SAT-Based Scheme to Determine Optimal Fix-free Codes. Data Compression Conference Proceedings.
169-178.
-
Singh, A., Gulati, K., & Khatri, S. P.
(2010).
Minimum Leakage Vector Computation using Weighted Partial MaxSAT. The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS. Midwest Symposium on Circuits and Systems.
201-204.
-
Gulati, K., Jayakumar, N., & Khatri, S. P.
(2009).
A PTL based highly testable structured ASIC design approach. 33-36.
-
Gopalani, S., Garg, R., Khatri, S. P., & Cheng, M.
(2009).
DFM-aware structured ASIC design. 29-32.
-
Croix, J. F., & Khatri, S. P.
(2009).
Introduction to GPU programming for EDA. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
276-280.
-
Gulati, K., & Khatri, S. P.
(2009).
Fault Table Generation using Graphics Processing Units. Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT.
60-67.
-
Garg, R., & Khatri, S. P.
(2009).
3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuit. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
498-+.
-
Karkala, V., Bollapalli, K. C., Garg, R., & Khatri, S. P.
(2009).
A PLL Design based on a Standing Wave Resonant Oscillator. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
511-+.
-
Kumar, R., Karkala, V., Garg, R., Jindal, T., & Khatri, S. P.
(2009).
A Radiation Tolerant Phase Locked Loop Design for Digital Electronics. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
505-+.
-
Kumar, R., Bollapalli, K. C., Garg, R., Soni, T., & Khatri, S. P.
(2009).
A Robust Pulsed Flip-flop and its use in Enhanced Scan Design. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
97-+.
-
Bollapalli, K. C., Garg, R., Gulati, K., & Khatri, S. P.
(2009).
On-chip Bidirectional Wiring for Heavily Pipe lined Systems using Network Coding. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
131-+.
-
Duperre, J., Burgett, G., Gargi, R., & Khatri, S. P.
(2009).
RF Receiver and Transmitter for Insect Mounted Sensor Platform. The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS. Midwest Symposium on Circuits and Systems.
264-+.
-
Alaparthi, S., Gulati, K., & Khatri, S. P.
(2009).
Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
2225-2228.
-
Paul, S., Garg, R., Khatri, S. P., & Vaidya, S.
(2009).
Design and Implementation of a Sub-threshold BFSK Transmitter. Proceedings - International Symposium on Quality Electronic Design, ISQED.
664-+.
-
Dash, R., Garg, R., Khatri, S. P., & Choi, G.
(2009).
SEU Hardened Clock Regeneration Circuits. Proceedings - International Symposium on Quality Electronic Design, ISQED.
806-813.
-
Gulati, K., Jayakumar, N., & Khatri, S. P.
(2009).
A PTL based Highly Testable Structured ASIC Design Approach. 145-+.
-
Gopalani, S., Garg, R., Khatri, S. P., & Cheng, M.
(2009).
DFM-aware Structured ASIC Design. 141-+.
-
Bollapalli, K. C., Wu, Y., Gulati, K., Khatri, S., & Calderbank, A. R.
(2009).
Highly parallel decoding of space-time codes on graphics processing units. 1262-1269.
-
Bollapalli, K. C., Garg, R., Gulati, K., & Khatri, S. P.
(2009).
Low Power and High Performance SRAM Design using Bank-based Selective Forward Body Bias. 441-444.
-
Gulati, K., & Khatri, S. P.
(2009).
Accelerating Statistical Static Timing Analysis Using Graphics Processing Units. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
260-265.
-
Garg, R., & Khatri, S. P.
(2009).
Efficient Analytical Determination of the SEU-induced Pulse Shape. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
461-467.
-
Gulati, K., Croix, J. F., Khatri, S. P., & Shastry, R.
(2009).
Fast Circuit Simulation on Graphics Processing Units. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
403-+.
-
Garg, R., & Khatri, S. P.
(2008).
A Novel, Highly SEU Tolerant Digital Circuit Design Approach. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
14-20.
-
Garg, R., Nagpal, C., & Khatri, S. P.
(2008).
A fast, analytical estimator for the SEU-induced pulse width in combinational designs. Design Automation Conference.
918-923.
-
Duan, C., Zhu, C., & Khatri, S. P.
(2008).
Forbidden transition free crosstalk avoidance CODEC design. Design Automation Conference.
986-991.
-
Gulati, K., & Khatri, S. P.
(2008).
Towards acceleration of fault simulation using Graphics Processing Units. Design Automation Conference.
822-827.
-
Das, S., & Khatri, S. P.
(2008).
A Timing-Driven Synthesis Approach of a Fast Four-Stage Hybrid Adder in Sum-of-Products. The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS. Midwest Symposium on Circuits and Systems.
507-+.
-
Garg, R., Li, P., & Khatri, S. P.
(2008).
Modeling dynamic stability of SRAMs in the presence of single event upsets (SEUs). IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
1788-1791.
-
Nagpal, C., Garg, R., & Khatri, S. P.
(2008).
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. Proceedings -Design, Automation and Test in Europe, DATE.
354-359.
-
Garg, R., Mallarapu, G., & Khatri, S. P.
(2008).
A Single-supply True Voltage Level Shifter. Proceedings -Design, Automation and Test in Europe, DATE.
1-6.
-
Cordero, V. H., & Khatri, S. P.
(2008).
Clock Distribution Scheme using Coplanar Transmission Lines. Proceedings -Design, Automation and Test in Europe, DATE.
1-6.
-
Duan, C., & Khatri, S. P.
(2008).
Energy Efficient and High Speed On-Chip Ternary Bus. Proceedings -Design, Automation and Test in Europe, DATE.
515-518.
-
Nagpal, C., Garg, R., & Khatri, S. P.
(2008).
A delay-efficient radiation-hard digital design approach using CWSP elements. Proceedings -Design, Automation and Test in Europe, DATE.
312-317.
-
Gopalani, S., Garg, R., Khatri, S. P., & Cheng, M.
(2008).
A lithography-friendly structured ASIC design approach. 315-320.
-
Venkatraman, A., Garg, R., & Khatri, S. P.
(2008).
A robust, fast pulsed flip-flop design. 119-122.
-
Garg, R., Mallarapu, G., & Khatri, S. P.
(2008).
A single-supply true voltage level shifter. Proceedings -Design, Automation and Test in Europe, DATE.
858-863.
-
Cordero, V. H., & Khatri, S. P.
(2008).
Clock distribution scheme using coplanar transmission lines. Proceedings -Design, Automation and Test in Europe, DATE.
864-869.
-
Duan, C., & Khatri, S. P.
(2008).
Energy efficient and high speed on-chip ternary bus. Proceedings -Design, Automation and Test in Europe, DATE.
1364-+.
-
Gulati, K., & Khatri, S. P.
(2008).
Improving FPGA routability using network coding. 147-150.
-
Paul, S., Garg, R., & Khatri, S. P.
(2008).
Pipelined network of PLA based circuit design. 213-218.
-
Das, S., & Khatri, S. P.
(2008).
A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. 635-640.
-
Das, S., & Khatri, S. P.
(2008).
A merged synthesis technique for fast arithmetic blocks involving sum-of-products and shifters. Proceedings of the IEEE International Conference on VLSI Design.
572-+.
-
Das, S., & Khatri, S. P.
(2008).
An inversion-based synthesis approach for area and power efficient arithmetic sum-of-products. Proceedings of the IEEE International Conference on VLSI Design.
653-+.
-
Das, S., & Khatri, S. P.
(2007).
A timing-driven hybrid-compression algorithm for faster sum-of-products. 273-278.
-
Das, S., & Khatri, S. P.
(2007).
Area-reducing sharing of mutually exclusive multiplier, MAC, adder and subtractor blocks. 269-272.
-
Menendez, E. R., Maduike, D. K., Garg, R., & Khatri, S. P.
(2007).
CMOS comparators for high-speed and low-power applications. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
76-+.
-
Garg, R., Jayakumar, N., & Khatri, S. P.
(2007).
On the improvement of statistical timing analysis. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
37-42.
-
Das, S., & Khatri, S. P.
(2007).
Timing-Driven Decomposition of a Fast Barrel Shifter. The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS. Midwest Symposium on Circuits and Systems.
574-577.
-
Goldberg, E., Gulati, K., & Khatri, S.
(2007).
Toggle Equivalence Preserving (TEP) Logic Optimization. 271-279.
-
Gulati, K., Jayakumar, N., & Khatri, S. P.
(2007).
A structured ASIC design approach using pass transistor logic. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
1787-1790.
-
Jayakumar, N., & Khatri, S. P.
(2007).
An algorithm to minimize leakage through simultaneous input vector control and circuit modification. Proceedings -Design, Automation and Test in Europe, DATE.
618-623.
-
Cobb, J., Garg, R., & Khatri, S. P.
(2007).
A Methodology for Interconnect Dimension Determination. 189-195.
-
Das, S., & Khatri, S. P.
(2007).
Generation of the Optimal Bit-Width Topology of the Fast Hybrid Adder in a Parallel Multiplier. 1-6.
-
Bhagawat, P., Ekambavanan, S., Das, S., Choi, G., & Khatri, S. P.
(2007).
VLSI implementation of a staggered sphere decoder design for MIMO detection. 228-235.
-
Kim, E., Jayakumar, N., Bhagwat, P., Selvarathinam, A., Choi, G., & Khatri, S. P.
(2006).
A high-speed fully-programmable VLSI decoder for regular LDPC codes. Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference).
3423-3426.
-
LaMeres, B. J., & Khatri, S. P.
(2006).
Bus stuttering TB An encoding technique to reduce inductive noise in off-chip data transmission. Proceedings -Design, Automation and Test in Europe, DATE.
520-+.
-
Duan, C., & Khatri, S. P.
(2006).
Computing during supply voltage switching in DVS enabled real-time processors. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
5115-+.
-
Garg, R., & Khatri, S. P.
(2006).
Generalized buffering of PTL logic stages using Boolean division. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
5615-+.
-
LaMeres, B. J., Garg, R., Gulati, K., & Khatri, S. P.
(2006).
Impedance matching techniques for VLSI packaging. 1009-1030.
-
Duan, C., Gulati, K., & Khatri, S. P.
(2006).
Memory-based cross-talk canceling CODECs for on-chip buses. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
1119-1122.
-
Garg, R., Jayakumar, N., Sanchez, M., Gupta, A., Gulati, K., & Khatri, S. P.
(2006).
A design flow to optimize circuit delay by using standard cells and PLAs. 217-222.
-
Shen, B., Khatri, S. P., & Zourntos, T.
(2006).
Implementation of MOSFET based capacitors for digital applications. 180-185.
-
Jayakumar, N., Khatri, S., Gulati, K., & Sprintson, A.
(2006).
Network Coding for Routability Improvement in VLSI. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
820-823.
-
Campbell, S. J., & Khatri, S. P.
(2006).
Resource and delay efficient matrix multiplication using newer FPGA devices. 308-311.
-
Garg, R., Jayakumar, N., Khatri, S. P., & Choi, G.
(2006).
A design approach for radiation-hard digital electronics. Design Automation Conference.
773-778.
-
Jayakumar, N., Garg, R., Gamache, B., & Khatri, S. P.
(2006).
A PLA based asynchronous micropipelining approach for subthreshold circuit design. Design Automation Conference.
419-424.
-
Garg, R., Jayakumar, N., Khatri, S. P., & Choi, G.
(2006).
A design approach for radiation-hard digital electronics. Design Automation Conference.
773-+.
-
Waghmode, M., Gulati, K., Khatri, S. P., & Shi, W.
(2006).
An Efficient, Scalable Hardware Engine for Boolean SATisfiability. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
326-331.
-
Jayakumar, N., Gulati, K., Khatri, S. P., & Sprintson, A.
(2006).
Network coding for routability improvement in VLSI. 74-+.
-
Jayakumar, N., Garg, R., Gamache, B., & Khatri, S. P.
(2006).
A PLA based asynchronous micropipelining approach for subthreshold circuit design. Design Automation Conference.
419-424.
-
LaMeres, B. J., Gulati, K., & Khatri, S. P.
(2006).
Controlling inductive cross-talk and power in off-chip buses using CODECs. 2017 22nd Asia and South Pacific Design Automation Conference (ASP-DAC).
850-855.
-
Gulati, K., Lovell, M., & Khatri, S. P.
(2006).
Efficient don't care computation for hierarchical designs. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
3037-3040.
-
Gulati, K., Jayakumar, N., & Khatri, S. P.
(2006).
Probabilistic method to determine the minimum leakage vector for combinational designs. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
2241-+.
-
Jayakumar, N., & Khatri, S. P.
(2005).
A Variation-tolerant sub-threshold design approach. Design Automation Conference.
716-719.
-
Van Culver, R., & Khatri, S. P.
(2005).
A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. 842-845.
-
Gulati, K., Jayakumar, N., & Khatri, S. P.
(2005).
An Algebraic Decision Diagram (ADD) based technique to find leakage histograms of combinational designs. Proceedings of the International Symposium on Low Power Electronics and Design.
111-114.
-
Valavi, J., Saluja, N., & Khatri, S. P.
(2005).
A boolean satisfiability based solution to the routing and wavelength assignment problem in optical telecommunication networks. IEEE International Conference on Communications.
1802-1806.
-
Jayakumar, N., Dhar, S., & Khatri, S. P.
(2005).
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. Design Automation Conference.
43-46.
-
LaMeres, B., & Khatri, S. P.
(2005).
Broadband Impedance Matching for Inductive Interconnect in VLSI Packages. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
683-688.
-
Saluja, N. S., & Khatri, S. P.
(2005).
Efficient SAT-based Combinational ATPG using Multi-level Don't-Cares. International Test Conference.
1-10.
-
LaMeres, B. J., & Khatri, S. P.
(2005).
Encoding-based Minimization of Inductive Cross-talk for Off-chip Data Transmission. Proceedings -Design, Automation and Test in Europe, DATE.
1318-1323.
-
Jayakumar, N., & Khatri, S. P.
(2005).
Minimum Energy Near-Threshold Network of PLA Based Design. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
399-404.
-
Hursey, E., Jayakumar, N., & Khatri, S. P.
(2005).
Non-Manhattan routing using a Manhattan router. Proceedings of the IEEE International Conference on VLSI Design.
445-450.
-
Venkataraman, G., Jayakumar, N., Hu, J., Li, P., Khatri, S., Rajaram, A., McGuinness, P., & Alpert, C.
(2005).
Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS.
592-596.
-
Ahmad, S., Jayakumar, N., Balasubramanian, V., Hursey, E., Khatri, S. P., & Mahapatra, R.
(2005).
X-routing using two Manhattan route instances. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
45-50.
-
Nagarajan, V., Jayakumar, N., Khatri, S., & Milenkovi, O.
(2004).
High-throughput VLSI implementations of iterative decoders and related code construction problems. 361-365.
-
Saluja, N., & Khatri, S. P.
(2004).
A robust algorithm for approximate Compatible Observability Don't Care (CODC) computation. Design Automation Conference.
422-427.
-
Jayakumar, N., & Khatri, S. P.
(2004).
A METAL and VIA maskset programmable VLSI design methodology using PLAs. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
590-594.
-
Kapoor, A., Jayakumar, N., & Khatri, S. P.
(2004).
A novel clock distribution and dynamic de-skewing methodology. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
626-631.
-
Duan, C., & Khatri, S. P.
(2004).
Exploiting Crosstalk to Speed up On-chip Buses. 778-783.
-
Jayakumar, N., & Khatri, S. P.
(2003).
An ASIC Design Methodology with Predictably Low Leakage, using Leakage-immune Standard Cells. Proceedings of the International Symposium on Low Power Electronics and Design.
128-133.
-
Gamache, B., Pfeffer, Z., & Khatri, S. P.
(2003).
A fast ternary cam design for ip networking applications. Proceedings - International Conference on Computer Communications and Networks, ICCCN.
434-439.
-
Bian, J., & Khatri, S. P.
(2003).
IP routing table compression using ESPRESSO-MV. IEEE International Conference on Networks, ICON.
167-172.
-
Das, S., & Khatri, S. P.
(2001).
A regularity-driven fast gridless detailed router for high frequency datapath designs. 130-135.
-
Gosti, W., Khatri, S. P., & Sangiovanni-Vincentelli, A. L.
(2001).
Addressing the timing closure problem by integrating logic optimization and placement. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
224-231.
-
Duan, C., Tirumala, A., & Khatri, S. P.
(2001).
Analysis and Avoidance of Cross-talk in On-Chip Buses. Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects.
133-138.
-
Sinha, S., Khatri, S. P., Brayton, R. K., & Sangiovanni-Vincentelli, A. L.
(2000).
Binary and multi-valued SPFD-based wire removal in PLA networks. 494-503.
-
Khatri, S. P., Brayton, R. K., & Sangiovanni-Vincentelli, A.
(2000).
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
412-418.
-
Brayton, R. K., & Khatri, S. P.
(1999).
Multi-valued logic synthesis. 196-205.
-
Khatri, S. P., Brayton, R. K., & Sangiovanni-Vincentelli, A. L.
(1999).
Sequential multi-valued network simplification using redundancy removal. 206-211.
-
Taran, S., Khatri, S. P., Yovine, S., Brayton, R. K., & Sangiovanni-Vincentelli, A.
(1998).
A timed automaton-based method for accurate computation of circuit delay in the presence of cross-talk. Lecture Notes in Artificial Intelligence.
149-166.
-
Jain, J., Narayan, A., Sangiovanni-Vincentelli, A., Coelho, C., Brayton, R. K., Khatri, S. P., & Fujita, M.
(1996).
Decomposition techniques for efficient ROBDD construction. Lecture Notes in Artificial Intelligence.
419-434.
-
Khatri, S. P., McMillan, K. L., Narayan, A., Brayton, R. K., Krishnan, S. C., & Sangiovanni-Vincentelli, A.
(1996).
Engineering change in a non-deterministic FSM setting. Design Automation Conference.
451-456.
-
Narayan, A., Khatri, S. P., Jain, J., Fujita, M., Brayton, R. K., & Sangiovanni-Vincentelli, A.
(1996).
Study of composition schemes for mixed apply/compose based construction of ROBDDs. 249-252.
-
Brayton, R. K., Hachtel, G. D., Sangiovanni-Vincentelli, A., Somenzi, F., Aziz, A., Cheng, S., ... Villa, T.
(1996).
VIS. 248-256.
-
Brayton, R. K., Hachtel, G. D., Sangiovanni-Vincentelli, A., Somenzi, F., Aziz, A., Cheng, S., ... Villa, T.
(1996).
VIS: A system for verification and synthesis. 428-432.
-
Scott, K. R., & Khatri, S. P.
(2022).
A Flash-based Digital to Analog Converter for Low Power Applications. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
1-8.
Research
co-principal investigator on
- RTML: Small: Real-Time Model-Based Bayesian Reinforcement Learning awarded by National Science Foundation - (Arlington, Virginia, United States) 2019 - 2022
- PFI-AIR-TT: Wearable Sleepwear for Quantitative Prognostication and Noninvasive Therapy of Obstructive Sleep Apnea awarded by National Science Foundation - (Arlington, Virginia, United States) 2015 - 2019
- Revolutionary Low Power Component Design for Man Portable Radiation Detectors awarded by United States Department of Defense - (Washington D.C., District of Columbia, United States) 2012 - 2016
Teaching
teaching activities
- ECEN403 Electrical Design Lab I Instructor
- ECEN403 Electrical Design Lab I Instructor
- ECEN404 Electrical Design Lab Ii Instructor
- ECEN449 Microprocsr Sys Dsgn Instructor
- ECEN485 Directed Studies Instructor
- ECEN491 Hnr-research Instructor
- ECEN684 Professional Internship Instructor
- ECEN684 Professional Internship: In-ab Instructor
- ECEN685 Directed Studies Instructor
- ECEN689 Sptp: Quantum & Logic Synth Instructor
- ECEN689 Sptp: Scal Dist Consen/appl Instructor
- ECEN691 Research Instructor
- ECEN699 Adv Vlsi Logic Synthesis Instructor
- ECEN749 Microprocessor Systems Design Instructor
Works By Students
chaired theses and dissertations
-
Bian, Kun (2013-12). Efficient Path Delay Test Generation with Boolean Satisfiability.
-
Bollapalli, Kalyana Chakravarthy (2011-02). IP Routing Table Compression Using TCAM and Distance-one Merge.
-
Cobb, Jeffrey Lee (2009-05). A robust window-based multi-node minimization technique using Boolean relations.
-
Ekambavanan, Sasidharan (2009-05). Encoding serial data for energy-delay-product and energy minimization.
-
Elshennawy, Amr (2014-11). An Asynchronous Network-On-Chip Router with Low Standby Power.
-
Garg, Rajesh (2007-09). Generalized buffering of pass transistor logic (PTL) stages using Boolean division and don't cares.
-
Garg, Rajesh (2010-07). Analysis and Design of Resilient VLSI Circuits.
-
Gulati, Kanupriya (2006-08). Computing leakage current distributions and determination of minimum leakage vectors for combinational designs.
-
Gulati, Kanupriya (2010-07). Hardware Acceleration of Electronic Design Automation Algorithms.
-
Jayakumar, Nikhil (2009-05). Minimizing and exploiting leakage in VLSI.
-
Karkala, Vinay (2011-10). A PLL Design Based on a Standing Wave Resonant Oscillator.
-
Kumar, Harsh (2016-11). A Plain-text Compression Technique with Fast Lookup Ability.
-
Kumar, Rajeev (2013-04). An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT.
-
Kumar, Rajesh (2011-10). A Radiation Tolerant Phase Locked Loop Design for Digital Electronics.
-
Lin, Pey Chang K (2013-06). Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks.
-
Mandal, Ayan (2013-05). Efficient Design and Clocking for a Network-on-Chip.
-
Murray, Luke (2014-10). Efficient On-Chip Power Supply Sampling to Improve Post-Silicon Debug.
-
Nagpal, Charu (2008-10). A delay-efficient radiation-hard digital design approach using code word state preserving (cwsp) elements.
-
Paul, Suganth (2009-05). Design and implementation of a sub-threshold wireless BFSK transmitter.
-
Poothamkurissi Swaminathan, Subramanian (2012-10). Timing Aware Partitioning for Multi-FPGA based Logic Simulation using Top-down Selective Flattening.
-
Singh, Karandeep (2007-09). Maximum and minimum sensitizable timing analysis using data dependent delays.
Background
education and training
- Ph.D. in Electrical Engineering, University of California, Berkeley - (Berkeley, California, United States) 1999
- M.S. in Electrical and Computer Engineering, The University of Texas at Austin - (Austin, Texas, United States) 1989
- B.S. in Electrical Engineering, Indian Institute of Technology Kanpur - (Kanpur, Uttar Pradesh, India) 1987
awards and honors
Contact
first name
- Sunil
has last name
- Khatri
mailing address
-
Texas A&M University
Electrical Engineering
3128 TAMU
College Station, TX 77843-3259
USA
Other
- sunilkhatri@tamu.edu