HR job title
- Professor
- Contact Info
- 1 979 845 8371
Khatri, Sunil Professor
Positions
My research areas include Computer-aided design of Very Large Scale Integration (VLSI) ICs, including logic and physical design automation.
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Overview
Publications
selected publications
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academic article
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Fairouz, A. A., Abusultan, M., Fedorov, V. V., & Khatri, S. P.
(2021).
Hardware Acceleration of Hash Operations in Modern Microprocessors. IEEE Transactions on Computers.
70(9), 1412-1426.
-
Douglass, A. J., & Khatri, S. P.
(2019).
Fast, Ring-Based Design of 3-D Stacked DRAM. IEEE Transactions on Very Large Scale Integration Systems.
-
Kawam, A. A., Khatri, S., & Datta, A.
(2018).
A GPU-CPU heterogeneous algorithm for NGS read alignment. International Journal of Computational Biology and Drug Design.
11(1/2), 52-52.
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Al Kawam, A., Khatri, S., & Datta, A.
(2017).
A Survey of Software and Hardware Approaches to Performing Read Alignment in Next Generation Sequencing. IEEE/ACM Transactions on Computational Biology and Bioinformatics.
14(6), 1202-1213.
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Shah, M. D., Marianno, C., Khatri, S. P., & Fisher, B. D.
(2017).
A Neutron Detector Using Integrated Circuits. 1(1), 3-7.
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Fedorov, V. V., Abusultan, M., & Khatri, S. P.
(2016).
FTCAM: An Area-Efficient Flash-Based Ternary CAM Design. IEEE Transactions on Computers.
65(8), 2652-2658.
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Kish, L. B., Granqvist, C., Khatri, S. P., & Peper, F.
(2016).
Response to Comment on Zero and negative energy dissipation at information-theoretic erasure. Journal of Computational Electronics.
15(1), 343-346.
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Kish, L. B., Granqvist, C., Khatri, S. P., & Peper, F.
(2016).
Zero and negative energy dissipation at information-theoretic erasure. Journal of Computational Electronics.
15(1), 335-339.
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Hearn, G., Marianno, C., Khatri, S., & Grypp, M.
(2014).
List mode with the ORTEC digiBASE-E. HEALTH PHYSICS.
106(2 Suppl 1), S12-S15.
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Croix, J. F., Khatri, S. P., & Gulati, K.
(2013).
Using GPUs to Accelerate CAD Algorithms. IEEE Design & Test.
30(1), 8-16.
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Savari, S. A., Yazdi, S., Abedini, N., & Khatri, S. P.
(2012).
On Optimal and Achievable Fix-Free Codes. 2011 IEEE INTERNATIONAL SYMPOSIUM ON INFORMATION THEORY PROCEEDINGS (ISIT).
58(8), 5112-5129.
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Kish, L. B., Khatri, S. P., Bezrukov, S. M., Peper, F., Gingl, Z., & Horvath, T.
(2011).
Noise-based Deterministic Logic and Computing: a Brief Survey. INTERNATIONAL JOURNAL OF UNCONVENTIONAL COMPUTING.
7(1-2), 101-113.
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Turker, D. Z., Khatri, S. P., & Sanchez-Sinencio, E.
(2011).
A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications. IEEE Transactions on Circuits and Systems I: Regular Papers.
58(6), 1225-1238.
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Kish, L. B., Khatri, S., & Horvath, T.
(2011).
Computation using noise-based logic: efficient string verification over a slow communication channel. European Physical Journal B: Condensed Matter and Complex Systems.
79(1), 85-90.
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KISH, L. B., KHATRI, S., & PEPER, F.
(2010).
INSTANTANEOUS NOISE-BASED LOGIC. Fluctuation and Noise Letters (FNL).
09(04), 323-330.
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GINGL, Z., KISH, L. B., & KHATRI, S. P.
(2010).
TOWARDS BRAIN-INSPIRED COMPUTING. Fluctuation and Noise Letters (FNL).
09(04), 403-412.
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Jayakumar, N., & Khatri, S. P.
(2010).
A Simultaneous Input Vector Control and Circuit Modification Technique to Reduce Leakage with Zero Delay Penalty. ACM Transactions on Design Automation of Electronic Systems.
16(1), 1-20.
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Ekambavanan, S., Garg, R., Khatri, S. P., & Narayanan, K. R.
(2009).
Encoding Serial Graphical Data for Energy-Delay Product/Energy Minimization. Journal of Low Power Electronics.
5(2), 157-172.
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Bollapalli, K. C., Garg, R., Gulati, K., & Khatri, S. P.
(2009).
Selective Forward Body Bias for High Speed and Low Power SRAMs. Journal of Low Power Electronics.
5(2), 185-195.
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Garg, R., Jayakumar, N., Khatri, S. P., & Choi, G. S.
(2009).
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. IEEE Transactions on Very Large Scale Integration Systems.
17(6), 781-792.
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Kish, L. B., Khatri, S., & Sethuraman, S.
(2009).
Noise-based logic hyperspace with the superposition of states in a single wire. Physics Letters A.
373(22), 1928-1934.
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Chunjie Duan, .., Calle, V., & Khatri, S. P.
(2009).
Efficient On-Chip Crosstalk Avoidance CODEC Design. IEEE Transactions on Very Large Scale Integration Systems.
17(4), 551-560.
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Gulati, K., Paul, S., Khatri, S. P., Patil, S., & Jas, A.
(2009).
FPGA-based hardware acceleration for Boolean satisfiability. ACM Transactions on Design Automation of Electronic Systems.
14(2), 1-11.
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Paul, S., Jayakumar, N., & Khatri, S. P.
(2009).
A Fast Hardware Approach for Approximate, Efficient Logarithm and Antilogarithm Computations. IEEE Transactions on Very Large Scale Integration Systems.
17(2), 269-277.
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Kapoor, A., Jayakumar, N., & Khatri, S. P.
(2008).
Dynamically De-Skewable Clock Distribution Methodology. IEEE Transactions on Very Large Scale Integration Systems.
16(9), 1220-1229.
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Das, S., & Khatri, S. P.
(2008).
Resource sharing among mutually exclusive sum-of-product blocks for area reduction. ACM Transactions on Design Automation of Electronic Systems.
13(3), 1-7.
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Gulati, K., Jayakumar, N., Khatri, S. P., & Walker, D.
(2008).
A probabilistic method to determine the minimum leakage vector for combinational designs in the presence of random PVT variations. Integration.
41(3), 399-412.
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Saluja, N., Gulati, K., & Khatri, S. P.
(2008).
SAT-based ATPG using multilevel compatible don't-cares. ACM Transactions on Design Automation of Electronic Systems.
13(2), 1-18.
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Das, S., & Khatri, S. P.
(2008).
A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. IEEE Transactions on Very Large Scale Integration Systems.
16(3), 326-331.
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Das, S., & Khatri, S. P.
(2008).
A Timing-Driven Approach to Synthesize Fast Barrel Shifters. IEEE Transactions on Circuits and Systems II: Express Briefs.
55(1), 31-35.
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Gulati, K., Waghmode, M., Khatri, S. P., & Shi, W.
(2008).
Efficient, scalable hardware engine for Boolean satisfiability and unsatisfiable core extraction. IET Computers and Digital Techniques.
2(3), 214-214.
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Lee, H., Cooper, R., Mika, B., Clayton, D., Garg, R., Gonzalez, J. M., ... Liang, H.
(2007).
Polymeric Sensors to Monitor Cockroach Locomotion. IEEE Sensors Journal.
7(12), 1698-1702.
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Nagarajan, V., Laendner, S., Jayakumar, N., Milenkovic, O., & Khatri, S. P.
(2007).
High-throughput VLSI Implementations of Iterative Decoders and Related Code Construction Problems. Journal of Signal Processing Systems.
49(1), 185-206.
-
Jayakumar, N., & Khatri, S. P.
(2007).
A Predictably Low-Leakage ASIC Design Style. IEEE Transactions on Very Large Scale Integration Systems.
15(3), 276-285.
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Khatri, S. P., Sinha, S., Brayton, R. K., & Sangiovanni-Vincentelli, A. L.
(2004).
SPFD-Based Wire Removal in Standard-Cell and Network-of-PLA Circuits. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
23(7), 1020-1030.
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Das, S., & Khatri, S. P.
(2002).
An efficient and regular routing methodology for datapath designs using net regularity extraction. IEEE Transactions on Computer - Aided Design of Integrated Circuits and Systems.
21(1), 93-101.
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Khatri, S. P., Mehrotra, A., Brayton, R. K., Otten, R., & Sangiovanni-Vincentelli, A.
(1999).
Novel VLSI layout fabric for deep sub-micron applications. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
491-496.
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Fairouz, A. A., Abusultan, M., Fedorov, V. V., & Khatri, S. P.
(2021).
Hardware Acceleration of Hash Operations in Modern Microprocessors. IEEE Transactions on Computers.
70(9), 1412-1426.
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book
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Mandal, A., Khatri, S. P., & Mahapatra, R.
(2014).
Source-Synchronous Networks-On-Chip. Ed. 9781461494058.
Springer New York.
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Lin, P., & Khatri, S. P.
(2014).
Logic Synthesis for Genetic Diseases. Ed. 9781461494294.
Springer New York.
-
Khatri, S. P., & Gulati, K.
(2011).
Advanced Techniques in Logic Synthesis, Optimizations and Applications. Springer New York.
-
Khatri, S. P., & Gulati, K.
(2011).
Introduction. Springer New York.
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Garg, R., & Khatri, S. P.
(2010).
Analysis and Design of Resilient VLSI Circuits. Springer US.
-
Gulati, K., & Khatri, S. P.
(2010).
Hardware Acceleration of EDA Algorithms. Springer US.
-
Jayakumar, N., Paul, S., Garg, R., Gulati, K., & Khatri, S. P.
(2010).
Minimizing and Exploiting Leakage in VLSI Design. Springer US.
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Duan, C., LaMeres, B. J., & Khatri, S. P.
(2010).
On and Off-Chip Crosstalk Avoidance in VLSI Design. Springer US.
-
Mandal, A., Khatri, S. P., & Mahapatra, R.
(2014).
Source-Synchronous Networks-On-Chip. Ed. 9781461494058.
Springer New York.
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chapter
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Khatri, S. P., Shenoy, N. V., Giomi, J. C., & Khouja, A.
(2017).
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology. Lavagno, L., Markov, I. L., Martin, G., & Scheffer, L. K. (Eds.),
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology.
(pp. 27-56).
CRC Press.
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Cobb, J. L., Gulati, K., & Khatri, S. P.
(2011).
A Robust Window-Based Multi-node Minimization Technique Using Boolean Relations. Advanced Techniques in Logic Synthesis, Optimizations and Applications.
(pp. 309-334).
Springer New York.
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Bollapalli, K. C., Khatri, S. P., & Kish, L. B.
(2011).
Digital Logic Using Non-DC Signals. Gulati, K. (Eds.),
Advanced Techniques in Logic Synthesis, Optimizations and Applications.
(pp. 383-400).
Springer New York.
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Khatri, S. P., & Shenoy, N. V.
(2006).
Logic synthesis. EDA for IC Implementation, Circuit Design, and Process Technology.
2-1-2-26.
-
Khatri, S. P., Shenoy, N. V., Giomi, J. C., & Khouja, A.
(2017).
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology. Lavagno, L., Markov, I. L., Martin, G., & Scheffer, L. K. (Eds.),
Electronic Design Automation for IC Implementation, Circuit Design, and Process Technology.
(pp. 27-56).
CRC Press.
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conference paper
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Bharathi, K., Hu, J., & Khatri, S. P.
(2020).
Scaled Population Subtraction for Approximate Computing. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
348-355.
-
Zhou, H. e., Khatri, S. P., Hu, J., & Liu, F.
(2019).
A Memory-Efficient Markov Decision Process Computation Framework Using BDD-based Sampling Representation. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
1-6.
-
Loyka, K., Zhou, H. e., & Khatri, S. P.
(2018).
A Homomorphic Encryption Scheme Based on Affine Transforms. GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI.
51-56.
-
Bharathi, K., Kumar, H., Fairouz, A., Al Kawam, A., & Khatri, S. P.
(2018).
A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
389-396.
-
Fairouz, A., Abusultan, M., Elshennawy, A., & Khatri, S. P.
(2018).
Comparing Leakage Reduction Techniques for an Asynchronous Network-on-Chip Router. Journal of Low Power Electronics.
414-427.
-
Douglass, A. J., & Khatri, S. P.
(2018).
Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
318-325.
-
Fairouz, A., & Khatri, S. P.
(2017).
An FPGA-Based Coprocessor for Hash Unit Acceleration. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
301-304.
-
Douglass, A. J., & Khatri, S. P.
(2017).
Fast, Ring-Based Design of 3D Stacked DRAM. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
665-672.
-
Zhou, H. e., Khatri, S. P., Hu, J., Liu, F., & Sze, C.
(2017).
Fast and Highly Scalable Bayesian MDP on a GPU Platform. 158-167.
-
Sharma, K., & Khatri, S.
(2017).
A Robust C-element Design with Enhanced Metastability Performance. 95-100.
-
Fairouz, A., Abusultan, M., & Khatri, S. P.
(2017).
Circuit Level Design of a Hardware Hash Unit for use in Modern Microprocessors. 101-106.
-
Abusultan, M., & Khatri, S. P.
(2017).
Design of a Flash-based Circuit for Multi-valued Logic. 41-46.
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Abusultan, M., & Khatri, S. P.
(2016).
A flash-based digital circuit design flow. 2011 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD).
1-6.
-
Fairouz, A., Abusultan, M., & Khatri, S. P.
(2016).
A novel hardware hash unit design for modern microprocessors. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
412-415.
-
Kottapalli, V., & Khatri, S.
(2016).
A practical methodology to validate the statistical behavior of bloom filters. 1-8.
-
Abusultan, M., & Khatri, S. P.
(2016).
Exploring static and dynamic flash-based FPGA design topologies. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
416-419.
-
Abusultan, M., & Khatri, S. P.
(2016).
Implementing low power digital circuits using flash devices. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
109-116.
-
Abusultan, M., & Khatri, S. P.
(2016).
A Ternary-Valued, Floating Gate Transistor-Based Circuit Design Approach. 2009 IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI.
719-724.
-
Zhou, H. e., Hu, J., Khatri, S. P., Liu, F., Sze, C., & Yousefi, M. R.
(2016).
GPU acceleration for Bayesian control of Markovian genetic regulatory networks. 304-307.
-
Abusultan, M., Chakravorty, S., & Khatri, S. P.
(2016).
A GPU-based Implementation of a Sensor Tasking Methodology. 1398-1405.
-
de Aguiar, J. M., & Khatri, S. P.
(2015).
Exploring the viability of stochastic computing. 391-394.
-
Kish, L. B., Khatri, S. P., Granqvist, C. G., & Smulko, J. M.
(2015).
Critical remarks on Landauer's principle of erasure-dissipation: Including notes on Maxwell demons and Szilard engines. 1-4.
-
Murray, L., & Khatri, S. P.
(2015).
An Efficient Approach to Sample On-Chip Power Supplies. 241-244.
-
Abusultan, M., & Khatri, S. P.
(2015).
Delay, Power and Energy Tradeoffs in Deep Voltage-scaled FPGAs. 111-114.
-
Fedorov, V. V., Abusultan, M., & Khatri, S. P.
(2014).
An area-efficient Ternary CAM design using floating gate transistors. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
55-60.
-
Elshennawy, A., & Khatri, S. P.
(2014).
An asynchronous Network-on-Chip router with low standby power. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
394-399.
-
Abusultan, M., & Khatri, S. P.
(2014).
Look-up Table Design for Deep Sub-threshold through Full-Supply Operation. 259-266.
-
Abusultan, M., & Khatri, S. P.
(2014).
A comparison of FinFET based FPGA LUT designs. GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI.
353-358.
-
Bian, K., Walker, D., & Khatri, S. P.
(2014).
Techniques to Improve the Efficiency of SAT Based Path Delay Test Generation. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
50-55.
-
Mandal, A., Bollapalli, K. C., Jayakumar, N., Khatri, S. P., & Mahaptra, R. N.
(2013).
A low-jitter phase-locked resonant clock generation and distribution scheme. 487-490.
-
Lin, P., & Khatri, S. P.
(2013).
Noise-based algorithms for functional equivalence and tautology checking. 235-240.
-
Elshennawy, A., Marianno, C. M., & Khatri, S. P.
(2013).
Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector. 329-330.
-
Kumar, R., & Khatri, S. P.
(2013).
Crosstalk Avoidance Codes for 3D VLSI. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1673-1678.
-
Bian, K., Walker, D., Khatri, S. P., & Lahiri, S.
(2013).
Mixed structural-functional path delay test generation and compaction. 18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS.
7-12.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2013).
A source-synchronous Htree-based network-on-chip. 161-166.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2013).
Exploring Topologies for a Source-synchronous Ring-based Network-on-Chip. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1026-1031.
-
Belsare, A., Liu, S., & Khatri, S.
(2013).
GPU implementation of a scalable non-linear congruential generator for cryptography applications. 89-94.
-
Lin, P., & Khatri, S. P.
(2012).
Determining gene function in boolean networks using boolean satisfiability. IEEE International Workshop on Genomic Signal Processing and Statistics : [proceedings]. IEEE International Workshop on Genomic Signal Processing and Statistics.
176-179.
-
Lin, P., & Khatri, S. P.
(2012).
Application of Max-SAT-based ATPG to optimal cancer therapy design. BMC GENOMICS.
S5-S5.
-
Kumar, R., Mandal, A., & Khatri, S. P.
(2012).
An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
195-200.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2012).
Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
482-483.
-
Swaminathan, S. P., Lin, P., & Khatri, S. P.
(2012).
Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
153-158.
-
Lin, P., & Khatri, S. P.
(2012).
Application of logic synthesis to the understanding and cure of genetic diseases. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
734-740.
-
Lin, P., Mandal, A., & Khatri, S. P.
(2012).
Boolean satisfiability using noise based logic. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
1256-1257.
-
Mandal, A., Khatri, S. P., & Mahapatra, R. N.
(2012).
A fast, source-synchronous ring-based network-on-chip design. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1489-1494.
-
Lin, P., Mandal, A., & Khatri, S. P.
(2012).
Boolean Satisfiability using Noise Based Logic. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
1256-1257.
-
Bhadviya, B., Mandal, A., & Khatri, S. P.
(2012).
Alleviating NBTI-induced failure in off-chip output drivers. 295-298.
-
Lin, P., & Khatri, S. P.
(2011).
Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG. IEEE International Workshop on Genomic Signal Processing and Statistics : [proceedings]. IEEE International Workshop on Genomic Signal Processing and Statistics.
87-90.
-
Lin, P., Ivanov, A., Johnson, B., & Khatri, S. P.
(2011).
A novel cryptographic key exchange scheme using resistors. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
451-452.
-
Kish, L. B., Khatri, S. P., Bezrukov, S. M., Peper, F., Gingl, Z., & Horvath, T.
(2011).
Noise-based information processing. 28-33.
-
Mandal, A., Jayakumar, N., Bollapalli, K., Khatri, S. P., & Mahapatra, R. N.
(2011).
An Automated Approach for Minimum Jitter Buffered H-Tree Construction. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
76-81.
-
Mandal, A., Karkala, V., Khatri, S. P., & Mahapatra, R. N.
(2011).
Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
82-87.
-
Karkala, V., Wanstrath, J., Lacour, T., & Khatri, S. P.
(2010).
Efficient arithmetic sum-of-product (SOP) based Multiple Constant Multiplication (MCM) for FFT. 2011 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD).
735-738.
-
Lin, P., & Khatri, S. P.
(2010).
Inference of gene predictor set using Boolean satisfiability. IEEE International Workshop on Genomic Signal Processing and Statistics : [proceedings]. IEEE International Workshop on Genomic Signal Processing and Statistics.
1-4.
-
Gope, D., Lin, P., & Khatri, S. P.
(2010).
Exploring a circuit design approach based on one-hot multi-valued domino logic. 2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3.
69-72.
-
Singh, A., Gulati, K., & Khatri, S. P.
(2010).
Minimum leakage vector computation using weighted partial MaxSAT. 2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3.
201-204.
-
Kumar, R., & Khatri, S. P.
(2010).
An efficient pulse flip-flop based launch-on-shift scan cell. 2005 IEEE International Symposium on Circuits and Systems (ISCAS).
4105-4108.
-
Gulati, K., & Khatri, S. P.
(2010).
Fault Table Computation on GPUs. Journal of Electronic Testing.
195-209.
-
Bollapalli, K. C., Khatri, S. P., & Kish, L. B.
(2010).
Implementing digital logic with sinusoidal supplies. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
315-318.
-
Abedini, N., Khatri, S. P., & Savari, S. A.
(2010).
A SAT-Based Scheme to Determine Optimal Fix-Free Codes. 2007 Data Compression Conference (DCC'07).
169-178.
-
Gulati, K., & Khatri, S. P.
(2010).
Boolean satisfiability on a graphics processor. 123-126.
-
Lin, P., & Khatri, S. P.
(2010).
VLSI implementation of a non-linear feedback shift register for high-speed cryptography applications. 381-384.
-
Gulati, K., Jayakumar, N., & Khatri, S. P.
(2009).
A PTL based highly testable structured ASIC design approach. 33-36.
-
Gopalani, S., Garg, R., Khatri, S. P., & Cheng, M.
(2009).
DFM-aware structured ASIC design. 29-32.
-
Croix, J. F., & Khatri, S. P.
(2009).
Introduction to GPU programming for EDA. 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
276-280.
-
Gulati, K., & Khatri, S. P.
(2009).
Fault table generation using Graphics Processing Units. 2009 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP.
60-67.
-
Garg, R., & Khatri, S. P.
(2009).
3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
498-504.
-
Karkala, V., Bollapalli, K. C., Garg, R., & Khatri, S. P.
(2009).
A PLL design based on a standing wave resonant oscillator. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
511-516.
-
Kumar, R., Karkala, V., Garg, R., Jindal, T., & Khatri, S. P.
(2009).
A radiation tolerant Phase Locked Loop design for digital electronics. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
505-510.
-
Kumar, R., Bollapalli, K. C., Garg, R., Soni, T., & Khatri, S. P.
(2009).
A robust pulsed flip-flop and its use in enhanced scan design. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
97-102.
-
Bollapalli, K. C., Garg, R., Gulati, K., & Khatri, S. P.
(2009).
On-chip bidirectional wiring for heavily pipelined systems using network coding. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
131-136.
-
Bollapalli, K., Wu, Y., Gulati, K., Khatri, S., & Calderbank, A. R.
(2009).
Highly parallel decoding of space-time codes on graphics processing units. 1262-1269.
-
Duperre, J., Burgettz, G., & Gargz, R.
(2009).
RF receiver and transmitter for insect mounted sensor platform. 2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3.
264-267.
-
Alaparthi, S., Gulati, K., & Khatri, S. P.
(2009).
Sorting binary numbers in hardware - A novel algorithm and its implementation. 2005 IEEE International Symposium on Circuits and Systems (ISCAS).
2225-2228.
-
Gulati, K., Jayakumar, N., & Khatri, S. P.
(2009).
A PTL based Highly Testable Structured ASIC Design Approach. 145-+.
-
Gopalani, S., Garg, R., Khatri, S. P., & Cheng, M.
(2009).
DFM-aware Structured ASIC Design. 141-+.
-
Paul, S., Garg, R., Khatriz, S. P., & Vaidya, S.
(2009).
Design and implementation of a sub-threshold BFSK transmitter. 2010 11th International Symposium on Quality Electronic Design (ISQED).
664-672.
-
Dash, R., Garg, R., Khatri, S. P., & Choi, G.
(2009).
SEU hardened clock regeneration circuits. 2010 11th International Symposium on Quality Electronic Design (ISQED).
806-813.
-
Gulati, K., & Khatri, S. P.
(2009).
Accelerating statistical static timing analysis using graphics processing units. 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC).
260-265.
-
Garg, R., & Khatri, S. P.
(2009).
Efficient analytical determination of the SEU-induced pulse shape. 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC).
461-467.
-
Gulati, K., Croix, J. F., Khatri, S. P., & Shastry, R.
(2009).
Fast circuit simulation on graphics processing units. 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC).
403-408.
-
Bollapalli, K. C., Garg, R., Gulati, K., & Khatri, S. P.
(2009).
Low power and high performance sram design using bank-based selective forward body bias. 441-444.
-
Garg, R., & Khatri, S. P.
(2008).
A novel, highly SEU tolerant digital circuit design approach. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
14-20.
-
Garg, R., Nagpal, C., & Khatri, S. P.
(2008).
A fast, analytical estimator for the SEU-induced pulse width in combinational designs. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
918-923.
-
Duan, C., Zhu, C., & Khatri, S. P.
(2008).
Forbidden transition free crosstalk avoidance CODEC design. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
986-991.
-
Das, S., & Khatri, S. P.
(2008).
A timing-driven synthesis approach of a fast four-stage hybrid adder in Sum-of-Products. 2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3.
507-510.
-
Garg, R., Peng Li, .., & Khatri, S. P.
(2008).
Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs). 2005 IEEE International Symposium on Circuits and Systems (ISCAS).
1788-1791.
-
Nagpal, C., Garg, R., & Khatri, S. P.
(2008).
A Delay-efficient Radiation-hard Digital Design Approach Using CWSP Elements. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
354-359.
-
Garg, R., Mallarapu, G., & Khatri, S. P.
(2008).
A Single-supply True Voltage Level Shifter. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1-6.
-
Cordero, V. H., & Khatri, S. P.
(2008).
Clock Distribution Scheme using Coplanar Transmission Lines. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1-6.
-
Duan, C., & Khatri, S. P.
(2008).
Energy Efficient and High Speed On-Chip Ternary Bus. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
515-518.
-
Nagpal, C., Garg, R., & Khatri, S. P.
(2008).
A delay-efficient radiation-hard digital design approach using CWSP elements. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
312-317.
-
Garg, R., Mallarapu, G., & Khatri, S. P.
(2008).
A single-supply true voltage level shifter. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
858-863.
-
Cordero, V. H., & Khatri, S. P.
(2008).
Clock distribution scheme using coplanar transmission lines. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
864-869.
-
Duan, C., & Khatri, S. P.
(2008).
Energy efficient and high speed on-chip ternary bus. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1364-+.
-
Gulati, K., & Khatri, S. P.
(2008).
Towards acceleration of fault simulation using Graphics Processing Units. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
822-827.
-
Das, S., & Khatri, S. P.
(2008).
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
572-577.
-
Das, S., & Khatri, S. P.
(2008).
A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions. 635-640.
-
Gopalani, S., Garg, R., Khatri, S. P., & Cheng, M.
(2008).
A lithography-friendly structured ASIC design approach. 315-320.
-
Venkatraman, A., Garg, R. F., & Khatri, S. P.
(2008).
A robust, fast pulsed flip-flop design. 119-122.
-
Das, S., & Khatri, S. P.
(2008).
An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
653-658.
-
Gulati, K., & Khatri, S. P.
(2008).
Improving FPGA routability using network coding. 147-150.
-
Paul, S., Garg, R., & Khatri, S. P.
(2008).
Pipelined network of PLA based circuit design. 213-218.
-
Das, S., & Khatri, S. P.
(2007).
A timing-driven hybrid-compression algorithm for faster sum-of-products. 273-278.
-
Das, S., & Khatri, S. P.
(2007).
Area-reducing sharing of mutually exclusive multiplier, MAC, adder and subtractor blocks. 269-272.
-
Das, S., & Khatri, S. P.
(2007).
Timing-driven decomposition of a fast barrel shifter. 2007 50TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3.
574-577.
-
Goldberg, E., Gulati, K., & Khatri, S.
(2007).
Toggle Equivalence Preserving (TEP) Logic Optimization. 271-279.
-
Gulati, K., Jayakumar, N., & Khatri, S. P.
(2007).
A Structured ASIC Design Approach Using Pass Transistor Logic. 2005 IEEE International Symposium on Circuits and Systems (ISCAS).
1787-1790.
-
Das, S., & Khatri, S. P.
(2007).
Generation of the Optimal Bit-Width Topology of the Fast Hybrid Adder in a Parallel Multiplier. 1-6.
-
Jayakumar, N., & Khatri, S. P.
(2007).
An Algorithm to Minimize Leakage through Simultaneous Input Vector Control and Circuit Modification. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1-6.
-
Cobb, J., Garg, R., & Khatri, S. P.
(2007).
A methodology for interconnect dimension determination. 189-195.
-
Bhagawat, P., Ekambavanan, S., Das, S., Choi, G., & Khatri, S. P.
(2007).
VLSI implementation of a staggered sphere decoder design for MIMO detection. 228-235.
-
LaMeres, B. J., Garg, R., Gulati, K., & Khatri, S. P.
(2006).
Impedance matching techniques for VLSI packaging. 1009-1030.
-
Garg, R., Jayakumar, N., Sanchez, M., Gupta, A., Gulati, K., & Khatri, S. P.
(2006).
A design flow to optimize circuit delay by using standard cells and PLAs. 217-222.
-
Shen, B., Khatri, S. P., & Zourntos, T.
(2006).
Implementation of MOSFET based capacitors for digital applications. 180-185.
-
Jayakumar, N., Khatri, S., Gulati, K., & Sprintson, A.
(2006).
Network Coding for Routability Improvement in VLSI. 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
820-823.
-
Campbell, S. J., & Khatri, S. P.
(2006).
Resource and delay efficient matrix multiplication using newer FPGA devices. 308-311.
-
Waghmode, M., Gulati, K., Khatri, S. P., & Shi, W.
(2006).
An Efficient, Scalable Hardware Engine for Boolean SATisfiability. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
326-331.
-
Menendez, E. R., Maduike, D. K., Garg, R., & Khatri, S. P.
(2006).
CMOS Comparators for High-Speed and Low-Power Applications. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
76-81.
-
Garg, R., Jayakumar, N., & Khatri, S. P.
(2006).
On the Improvement of Statistical Timing Analysis. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
37-42.
-
Garg, R., Jayakumar, N., Khatri, S. P., & Choi, G.
(2006).
A design approach for radiation-hard digital electronics. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
773-+.
-
Kim, E., Jayakumar, N., Bhagwat, P., Selvarathinam, A., Choi, G., & Khatri, S. P.
(2006).
A high-speed fully-programmable VLSI decoder for regular LDPC codes. 1999 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings. ICASSP99 (Cat. No.99CH36258).
3423-3426.
-
LaMeres, B. J., & Khatri, S. P.
(2006).
Bus stuttering TB An encoding technique to reduce inductive noise in off-chip data transmission. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
520-+.
-
Duan, C., & Khatri, S. P.
(2006).
Computing during supply voltage switching in DVS enabled real-time processors. 2005 IEEE International Symposium on Circuits and Systems (ISCAS).
5115-+.
-
Garg, R., & Khatri, S. P.
(2006).
Generalized buffering of PTL logic stages using Boolean division. 2005 IEEE International Symposium on Circuits and Systems (ISCAS).
5615-+.
-
Duan, C., Gulati, K., & Khatri, S. P.
(2006).
Memory-based cross-talk canceling CODECs for on-chip buses. 2005 IEEE International Symposium on Circuits and Systems (ISCAS).
1119-1122.
-
Jayakumar, N., Gulati, K., Khatri, S. P., & Sprintson, A.
(2006).
Network coding for routability improvement in VLSI. 74-+.
-
Jayakumar, N., Garg, R., Gamache, B., & Khatri, S. P.
(2006).
A PLA based asynchronous micropipelining approach for subthreshold circuit design. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
419-424.
-
Jayakuma, N., Garg, R., Gamache, B., & Khatri, S. P.
(2006).
A PLA based asynchronous micropipelining approach for subthreshold circuit design. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
419-424.
-
Gulati, K., Jayakumar, N., & Khatri, S. P.
(2006).
A Probabilistic Method to Determine the Minimum Leakage Vector for Combinational Designs. 2005 IEEE International Symposium on Circuits and Systems (ISCAS).
4 pp.-2244-+.
-
Garg, R., Jayakumar, N., Khatri, S. P., & Choi, G.
(2006).
A design approach for radiation-hard digital electronics. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
773-778.
-
LaMeres, B. J., Gulati, K., & Khatri, S. P.
(2006).
Controlling inductive cross-talk and power in off-chip buses using CODECs. 2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC).
850-855.
-
Gulati, K., Khatri, S. P., & Lovell, M.
(2006).
Efficient Don't Care Computation for Hierarchical Designs. 2005 IEEE International Symposium on Circuits and Systems (ISCAS).
4 pp.-3040-3040.
-
Jayakumar, N., & Khatri, S. P.
(2005).
A Variation-tolerant sub-threshold design approach. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
716-719.
-
Van Culver, R., & Khatri, S. P.
(2005).
A dynamic voltage scaling algorithm for energy reduction in hard real-time systems. 842-845.
-
Gulati, K., Jayakumar, N., & Khatri, S. P.
(2005).
An Algebraic Decision Diagram (ADD) based technique to find leakage histograms of combinational designs. 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED).
111-114.
-
Valavi, J., Saluja, N., & Khatri, S. P.
(2005).
A boolean satisfiability based solution to the routing and wavelength assignment problem in optical telecommunication networks. 2001 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-10, CONFERENCE RECORD.
1802-1806.
-
Nikhil Jayakumar, .., Sandeep Dhar, .., & Sunil P Khatri.
(2005).
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
43-46.
-
La Meres, B., & Khairi, S. P.
(2005).
Broadband impedance matching for inductive interconnect in VLSI packages. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
683-688.
-
Saluja, N. S., & Khatri, S. P.
(2005).
Efficient SAT-based combinational ATPG using multi-level don't-cares. 2013 IEEE International Test Conference (ITC).
1-10.
-
LaMeres, B. J., & Khatri, S. P.
(2005).
Encoding-Based Minimization of Inductive Cross-Talk for Off-Chip Data Transmission. 2006 DESIGN AUTOMATION AND TEST IN EUROPE, VOLS 1-3, PROCEEDINGS.
1318-1323.
-
Jayakumar, N., & Khatri, S. R.
(2005).
Minimum energy near-threshold network of PLA based design. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
399-404.
-
Hursey, E., Jayakumar, N., & Khatri, S. P.
(2005).
Non-Manhattan routing using a Manhattan router. 16TH INTERNATIONAL CONFERENCE ON VLSI DESIGN, PROCEEDINGS.
445-450.
-
Venkataraman, G., Jayakumar, N., Jiang Hu, .., Peng Li, .., & Khatri, S.
(2005).
Practical techniques to reduce skew and its variations in buffered clock networks. ICCAD-2005: INTERNATIONAL CONFERENCE ON COMPUTER AIDED DESIGN, DIGEST OF TECHNICAL PAPERS.
592-596.
-
Ahmad, S., Jayakumar, N., Balasubramanian, V., Hursey, E., Khatri, S. P., & Mahapatra, R.
(2005).
X-routing using two Manhattan route instances. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
45-50.
-
Nagarajan, V., Jayakumar, N., Khatri, S., & Milenkovi, O.
(2004).
High-throughput VLSI implementations of iterative decoders and related code construction problems. 361-365.
-
Saluja, N., & Khatri, S. P.
(2004).
A robust algorithm for approximate Compatible Observability Don't Care (CODC) computation. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
422-427.
-
Jayakumar, N., & Khatri, S. P.
(2004).
A metal and via maskset programmable VLSI design methodology using PLAs. 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
590-594.
-
Kapoor, A., Jayakumar, N., & Khatri, S. P.
(2004).
A novel clock distribution and dynamic de-skewing methodology. 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
626-631.
-
Duan, C., & Khatri, S. P.
(2004).
Exploiting crosstalk to speed up on-chip buses. 778-783.
-
Jayakumar, N., & Khatri, S. P.
(2003).
An ASIC Design Methodology with Predictably Low Leakage, using Leakage-immune Standard Cells. 2015 IEEE/ACM INTERNATIONAL SYMPOSIUM ON LOW POWER ELECTRONICS AND DESIGN (ISLPED).
128-133.
-
Gamache, B., Pfeffer, Z., & Khatri, S. P.
(2003).
A fast ternary CAM design for IP networking applications. 2011 20TH INTERNATIONAL CONFERENCE ON COMPUTER COMMUNICATIONS AND NETWORKS (ICCCN).
434-439.
-
Bian, J., & Khatri, S. P.
(2003).
IP routing table compression using ESPRESSO-MV. 2013 19TH IEEE INTERNATIONAL CONFERENCE ON NETWORKS (ICON).
167-172.
-
Das, S., & Khatri, S. P.
(2001).
A regularity-driven fast gridless detailed router for high frequency datapath designs. 130-135.
-
Gosti, W., Khatri, S. P., & Sangiovanni-Vincentelli, A. L.
(2001).
Addressing the timing closure problem by integrating logic optimization and placement. 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
224-231.
-
Chunjie Duan, .., Anup Tirumala, .., & Khatri, S. P.
(2001).
Analysis and avoidance of cross-talk in on-chip buses. Proceedings - Symposium on the High Performance Interconnects, Hot Interconnects.
133-138.
-
Sinha, S., Khatri, S. P., Brayton, R. K., & Sangiovanni-Vincentelli, A. L.
(2000).
Binary and multi-valued SPFD-based wire removal in PLA networks. 494-503.
-
Khatri, S. P., Brayton, R. K., & Sangiovanni-Vincentelli, A.
(2000).
Cross-talk immune VLSI design using a network of PLAs embedded in a regular layout fabric. 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).
412-418.
-
Brayton, R. K., & Khatri, S. P.
(1999).
Multi-valued logic synthesis. 196-205.
-
Khatri, S. P., Brayton, R. K., & Sangiovanni-Vincentelli, A. L.
(1999).
Sequential multi-valued network simplification using redundancy removal. 206-211.
-
Taran, S., Khatri, S. P., Yovine, S., Brayton, R. K., & Sangiovanni-Vincentelli, A.
(1998).
A timed automaton-based method for accurate computation of circuit delay in the presence of cross-talk. ADVANCED COMPUTING STRATEGIES FOR ENGINEERING, PT II.
149-166.
-
Jain, J., Narayan, A., Sangiovanni-Vincentelli, A., Coelho, C., Brayton, R. K., Khatri, S. P., & Fujita, M.
(1996).
Decomposition techniques for efficient ROBDD construction. ADVANCED COMPUTING STRATEGIES FOR ENGINEERING, PT II.
419-434.
-
Khatri, S. P., McMillan, K. L., Narayan, A., Brayton, R. K., Krishnan, S. C., & Sangiovanni-Vincentelli, A.
(1996).
Engineering change in a non-deterministic FSM setting. 2007 44TH ACM/IEEE DESIGN AUTOMATION CONFERENCE, VOLS 1 AND 2.
451-456.
-
Narayan, A., Khatri, S. P., Jain, J., Fujita, M., Brayton, R. K., & Sangiovanni-Vincentelli, A.
(1996).
Study of composition schemes for mixed apply/compose based construction of ROBDDs. 249-252.
-
Brayton, R. K., Hachtel, G. D., Sangiovanni-Vincentelli, A., Somenzi, F., Aziz, A., Cheng, S., ... Villa, T.
(1996).
VIS. ADVANCED COMPUTING STRATEGIES FOR ENGINEERING, PT II.
248-256.
-
Brayton, R. K., Hachtel, G. D., Sangiovanni-Vincentelli, A., Somenzi, F., Aziz, A., Cheng, S., ... Villa, T.
(1996).
VIS: A system for verification and synthesis. ADVANCED COMPUTING STRATEGIES FOR ENGINEERING, PT II.
428-432.
-
Bharathi, K., Hu, J., & Khatri, S. P.
(2020).
Scaled Population Subtraction for Approximate Computing. 2009 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN.
348-355.
Research
co-principal investigator on
- RTML: Small: Real-Time Model-Based Bayesian Reinforcement Learning awarded by National Science Foundation - (Arlington, Virginia, United States) 2019 - 2022
- PFI-AIR-TT: Wearable Sleepwear for Quantitative Prognostication and Noninvasive Therapy of Obstructive Sleep Apnea awarded by National Science Foundation - (Arlington, Virginia, United States) 2015 - 2019
- Revolutionary Low Power Component Design for Man Portable Radiation Detectors awarded by United States Department of Defense - (Washington D.C., District of Columbia, United States) 2012 - 2016
Teaching
teaching activities
- ECEN403 Electrical Design Lab I Instructor
- ECEN403 Electrical Design Lab I Instructor
- ECEN404 Electrical Design Lab Ii Instructor
- ECEN449 Microprocsr Sys Dsgn Instructor
- ECEN485 Directed Studies Instructor
- ECEN491 Hnr-research Instructor
- ECEN684 Professional Internship Instructor
- ECEN684 Professional Internship: In-ab Instructor
- ECEN685 Directed Studies Instructor
- ECEN689 Sptp: Quantum & Logic Synth Instructor
- ECEN691 Research Instructor
- ECEN699 Adv Vlsi Logic Synthesis Instructor
- ECEN749 Microprocessor Systems Design Instructor
Works By Students
chaired theses and dissertations
-
Bian, Kun (2013-12). Efficient Path Delay Test Generation with Boolean Satisfiability.
-
Bollapalli, Kalyana Chakravarthy (2009-12). IP Routing Table Compression Using TCAM and Distance-one Merge.
-
Cobb, Jeffrey Lee (2007-12). A robust window-based multi-node minimization technique using Boolean relations.
-
Ekambavanan, Sasidharan (2007-08). Encoding serial data for energy-delay-product and energy minimization.
-
Elshennawy, Amr (2014-12). An Asynchronous Network-On-Chip Router with Low Standby Power.
-
Garg, Rajesh (2003-05). Generalized buffering of pass transistor logic (PTL) stages using Boolean division and don't cares.
-
Garg, Rajesh (2009-05). Analysis and Design of Resilient VLSI Circuits.
-
Gulati, Kanupriya (2003-05). Computing leakage current distributions and determination of minimum leakage vectors for combinational designs.
-
Gulati, Kanupriya (2009-12). Hardware Acceleration of Electronic Design Automation Algorithms.
-
Jayakumar, Nikhil (2007-05). Minimizing and exploiting leakage in VLSI.
-
Karkala, Vinay (2010-08). A PLL Design Based on a Standing Wave Resonant Oscillator.
-
Kumar, Harsh (2016-12). A Plain-text Compression Technique with Fast Lookup Ability.
-
Kumar, Rajeev (2013-05). An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT.
-
Kumar, Rajesh (2010-08). A Radiation Tolerant Phase Locked Loop Design for Digital Electronics.
-
Lin, Pey Chang K (2013-08). Application of Logic Synthesis Toward the Inference and Control of Gene Regulatory Networks.
-
Mandal, Ayan (2013-05). Efficient Design and Clocking for a Network-on-Chip.
-
Murray, Luke (2014-12). Efficient On-Chip Power Supply Sampling to Improve Post-Silicon Debug.
-
Nagpal, Charu (2008-05). A delay-efficient radiation-hard digital design approach using code word state preserving (cwsp) elements.
-
Paul, Suganth (2007-12). Design and implementation of a sub-threshold wireless BFSK transmitter.
-
Poothamkurissi Swaminathan, Subramanian (2012-08). Timing Aware Partitioning for Multi-FPGA based Logic Simulation using Top-down Selective Flattening.
-
Singh, Karandeep (2003-05). Maximum and minimum sensitizable timing analysis using data dependent delays.
Background
education and training
- Ph.D. in Electrical Engineering, University of California, Berkeley - (Berkeley, California, United States) 1999
- M.S. in Electrical and Computer Engineering, The University of Texas at Austin - (Austin, Texas, United States) 1989
- B.S. in Electrical Engineering, Indian Institute of Technology Kanpur - (Kanpur, Uttar Pradesh, India) 1987
awards and honors
Contact
first name
- Sunil
has last name
- Khatri
mailing address
-
Texas A&M University
Electrical Engineering
3128 TAMU
College Station, TX 77843-3259
USA
Other
- sunilkhatri@tamu.edu