A PLL design based on a standing wave resonant oscillator Conference Paper uri icon

abstract

  • In this paper, we present a new continuously variable high frequency standing wave oscillator, and demonstrate its use in generating the phase locked clock signal of a digital IC. The ring based standing wave resonant oscillator is implemented with a plurality of wires connected in a mobius configuration, with a cross coupled inverter pair connected across the wires. The oscillation frequency can be modulated by two means. Coarse modification is achieved by altering the number of wires in the ring that participate in the oscillation, by driving a digital word to a set of passgates which are connected to each wire in the ring. Fine tuning of the oscillation frequency is achieved by varying the body bias voltage of both the PMOS transistors in the cross coupled inverter pair which sustains the oscillations in the resonant ring. We nave validated our PLL design in a 90nm process technology. 3D parasitic RLCs for our oscillator simulations were extracted, with skin effect accounted for. Our PLL has been implemented to provide a frequency locking range from 6 GHz to 9 GHz, with a center frequency of 7.5 GHz. The oscillator alone consumes about 25 mW of power, and the complete PLL consumes a power of 28.5 mW. The observed jitter of the PLL is 2.56%. 2009 IEEE.

name of conference

  • 2009 IEEE International Conference on Computer Design (ICCD 2009)

published proceedings

  • 2009 IEEE International Conference on Computer Design

author list (cited authors)

  • Karkala, V., Bollapalli, K. C., Garg, R., & Khatri, S. P.

citation count

  • 9

complete list of authors

  • Karkala, Vinay||Bollapalli, Kalyana C||Garg, Rajesh||Khatri, Sunil P

publication date

  • October 2009

publisher