publication venue for
- Performance Driven Global Routing Through Gradual Refinement. 481-483. 2001
- Scaled Population Subtraction for Approximate Computing 2020
- Red Teaming a Multi-colored Bluetooth Bulb 2019
- SpecLock: Speculative Lock Forwarding 2019
- A Plain-text Incremental Compression (PIC) Technique with Fast Lookup Ability 2018
- Synchronization of Ring-based Resonant Standing Wave Oscillators for 3D Clocking Applications 2018
- An FPGA-based Coprocessor for Hash Unit Acceleration 2017
- Fast, Ring-based Design of 3D Stacked DRAM 2017
- A Novel Hardware Hash Unit Design for Modern Microprocessors 2016
- Exploring Static and Dynamic Flash-based FPGA Design Topologies 2016
- Implementing Low Power Digital Circuits using Flash Devices 2016
- An Area-efficient Ternary CAM Design using Floating Gate Transistors 2014
- An Asynchronous Network-on-Chip Router with Low Standby Power 2014
- Engineering Crossbar based Emerging Memory Technologies 2012
- Maximizing Crosstalk-Induced Slowdown during Path Delay Test 2012
- An Efficient Arithmetic Sum-of-Product (SOP) based Multiplication Approach for FIR Filters and DFT 2012
- Architectural Simulations of a Fast, Source-Synchronous Ring-based Network-on-Chip Design 2012
- Timing Aware Partitioning for Multi-FPGA Based Logic Simulation Using Top-down Selective Hierarchy Flattening 2012
- Track Assignment Considering Crosstalk-induced Performance Degradation 2012
- WaveSync: A Low-Latency Source Synchronous Bypass Network-On-Chip Architecture 2012
- A Novel Cryptographic Key Exchange Scheme using Resistors 2011
- An Optimized Scaled Neural Branch Predictor 2011
- Blue team red team approach to hardware trust assessment 2011
- 3D Simulation and Analysis of the Radiation Tolerance of Voltage Scaled Digital Circuit 2009
- A Distributed Concurrent On-Line Test Scheduling Protocol for Many-Core NoC-Based Systems 2009
- A PLL Design based on a Standing Wave Resonant Oscillator 2009
- A Radiation Tolerant Phase Locked Loop Design for Digital Electronics 2009
- A Robust Pulsed Flip-flop and its use in Enhanced Scan Design 2009
- Efficient Calibration of Thermal Models based on Application Behavior 2009
- On-chip Bidirectional Wiring for Heavily Pipe lined Systems using Network Coding 2009
- A Novel, Highly SEU Tolerant Digital Circuit Design Approach 2008
- CMOS comparators for high-speed and low-power applications 2007
- Dynamically Compressible Context Architecture for Low Power Coarse-Grained Reconfigurable Array 2007
- On the improvement of statistical timing analysis 2007
- Effective Dynamic Thermal Management for MPEG-4 Decoding 2007
- Implementation and Evaluation of On-Chip Network Architectures 2006
- An Efficient, Scalable Hardware Engine for Boolean SATisfiability 2006
- A low-overhead virtual rail technique for SRAM leakage power reduction 2005
- Broadband Impedance Matching for Inductive Interconnect in VLSI Packages 2005
- Minimum Energy Near-Threshold Network of PLA Based Design 2005
- X-routing using two Manhattan route instances 2005
- Low-density parity-check decoder architecture for high throughput optical fiber channels 2003
- A simple yet effective merging scheme for prescribed-skew clock routing 2003
- Hierarchical simulation of a multiprocessor architecture 2000
- Design methodology for a 1.0 GHz microprocessor 1998
- Circuit design techniques for a gigahertz integer microprocessor 1998