publication venue for
- Performance driven global routing through gradual refinement. 481-483. 2001
- Scaled Population Subtraction for Approximate Computing 2020
- Red Teaming a Multi-colored Bluetooth Bulb 2019
- SpecLock: Speculative Lock Forwarding 2019
- A Plain-Text Incremental Compression (PIC) Technique with Fast Lookup Ability 2018
- Synchronization of Ring-Based Resonant Standing Wave Oscillators for 3D Clocking Applications 2018
- An FPGA-Based Coprocessor for Hash Unit Acceleration 2017
- Fast, Ring-Based Design of 3D Stacked DRAM 2017
- A novel hardware hash unit design for modern microprocessors 2016
- Exploring static and dynamic flash-based FPGA design topologies 2016
- Implementing low power digital circuits using flash devices 2016
- An area-efficient Ternary CAM design using floating gate transistors 2014
- An asynchronous Network-on-Chip router with low standby power 2014
- An efficient arithmetic Sum-of-Product (SOP) based multiplication approach for FIR filters and DFT 2012
- Architectural simulations of a fast, source-synchronous ring-based Network-on-Chip design 2012
- Engineering crossbar based emerging memory technologies 2012
- Maximizing crosstalk-induced slowdown during path delay test 2012
- Timing aware partitioning for multi-FPGA based logic simulation using top-down selective hierarchy flattening 2012
- Track assignment considering crosstalk-induced performance degradation 2012
- A novel cryptographic key exchange scheme using resistors 2011
- An optimized scaled neural branch predictor 2011
- Blue team red team approach to hardware trust assessment 2011
- 3D simulation and analysis of the radiation tolerance of voltage scaled digital circuit 2009
- A PLL design based on a standing wave resonant oscillator 2009
- A distributed concurrent on-line test scheduling protocol for many-core NoC-based systems 2009
- A radiation tolerant Phase Locked Loop design for digital electronics 2009
- A robust pulsed flip-flop and its use in enhanced scan design 2009
- Efficient calibration of thermal models based on application behavior 2009
- On-chip bidirectional wiring for heavily pipelined systems using network coding 2009
- A novel, highly SEU tolerant digital circuit design approach 2008
- Dynamically compressible context architecture for low power coarse-grained reconfigurable array 2007
- Effective Dynamic Thermal Management for MPEG-4 Decoding 2007
- An Efficient, Scalable Hardware Engine for Boolean SATisfiability 2006
- CMOS Comparators for High-Speed and Low-Power Applications 2006
- Implementation and Evaluation of On-Chip Network Architectures 2006
- On the Improvement of Statistical Timing Analysis 2006
- A Low-Overhead Virtual Rail Technique for SRAM Leakage Power Reduction 2005
- Broadband impedance matching for inductive interconnect in VLSI packages 2005
- Minimum energy near-threshold network of PLA based design 2005
- X-routing using two Manhattan route instances 2005
- A simple yet effective merging scheme for prescribed-skew clock routing 2003
- Low-density parity-check decoder architecture for high throughput optical fiber channels 2003
- Hierarchical simulation of a multiprocessor architecture 2000
- Circuit design techniques for a gigahertz integer microprocessor 1998