Hierarchical simulation of a multiprocessor architecture Conference Paper

abstract

• When proposing new architectural enhancements, it is also important to account for the hardware complexity. To achieve this goal, we propose to model the new design in a hardware description language (HDL), synthesize the HDL code, and infer a realistic clock cycle which will be used in subsequent simulations. For accurate results, we develop a two-level hierarchical simulation technique, where an execution driven simulator (RSIM) and an HDL simulator (Verilog-XL) are coupled together to evaluate an entire system. We detail the simulation process and show its impact on the design of an interconnect switch architecture for CC-NUMA multiprocessors.

name of conference

• Proceedings 2000 International Conference on Computer Design

authors

• Mahapatra, Rabinarayan

published proceedings

• 2000 IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS & PROCESSORS, PROCEEDINGS

author list (cited authors)

• Pirvu, M., Bhuyan, L., & Mahapatra, R.

citation count

• 2

complete list of authors

• Pirvu, M||Bhuyan, L||Mahapatra, R

publication date

• January 2000

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Conference on Computer Design - VLSI in Computers and Processors  Journal

keywords

• 33 Built Environment And Design
• 3301 Architecture
• 40 Engineering
• 4008 Electrical Engineering
• Bioengineering

Digital Object Identifier (DOI)

• 10.1109/ICCD.2000.878349

International Standard Book Number (ISBN) 10

• 0-7695-0801-4

start page

• 585

end page

• 588

URL

• http://dx.doi.org/10.1109/iccd.2000.878349