An Area-efficient Ternary CAM Design using Floating Gate Transistors Conference Paper

abstract

• 2014 IEEE. This paper presents a Ternary Content-addressable Memory (TCAM) design which is based on the use of floating-gate (flash) transistors. TCAMs are extensively used in high speed IP networking, and are commonly found in routers in the internet core. Traditional TCAM ICs are built using CMOS devices, and a single TCAM cell utilizes 17 transistors. In contrast, our TCAM cell utilizes only 2 flash transistors, thereby significantly reducing circuit area. We cover the chip-level architecture of the TCAMIC briefly, focusing mainly on the TCAMblock which does fast parallel IP routing table lookup. Our flash based TCAM block is simulated in SPICE, and we show that it has a significantly lowered area compared to a CMOS based TCAMblock, with a speed that can meet current (400 Gb/s) data rates that are found in the internet core.

name of conference

• 2014 IEEE 32nd International Conference on Computer Design (ICCD)

authors

• Khatri, Sunil

published proceedings

• 2014 32ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER DESIGN (ICCD)

author list (cited authors)

• Fedorov, V. V., Abusultan, M., & Khatri, S. P.

citation count

• 12

complete list of authors

• Fedorov, Viacheslav V||Abusultan, Monther||Khatri, Sunil P

publication date

• October 2014

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Conference on Computer Design - VLSI in Computers and Processors  Journal

Digital Object Identifier (DOI)

• 10.1109/iccd.2014.6974662

International Standard Book Number (ISBN) 13

• 9781479964925

start page

• 55

end page

• 60

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ficcd.2014.6974662