A robust pulsed flip-flop and its use in enhanced scan design
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Delay faults are frequently encountered in nanometer technologies. Therefore, it is critical to detect these faults during factory test. Testing for a delay fault requires the application of a pair of test vectors in an at-speed manner. To maximize the delay fault detection capability, it is desired that the vectors in this pair are independent. Independent vector pairs cannot always be applied to a circuit implemented with standard scan design approaches. However, this can be achieved by using enhanced scan flip-flops, which store two bits of data. This paper has two contributions. First, we develop a pulsed flip-flop (PFF) design. Second, we present an enhanced scan flipflop design, based on our PFF circuit. We have compared the performance of our pulse based flip-flop with recently published pulse based flip-flop designs, as well as a traditional masterslave D flip-flop. Our PFF shows significant improvements in power and timing compared to the other designs. Our pulse based enhanced scan flip-flop (PESFF) has 13% lower power dissipation and 26% better timing than a conventional D flipflop based enhanced scan flip-flop (DESFF). The layout area of our PESFF is 5.2% smaller than the DESFF. Monte Carlo simulations demonstrate that our design is more robust to process variations than the DESFF. 2009 IEEE.
name of conference
2009 IEEE International Conference on Computer Design (ICCD 2009)
2009 IEEE International Conference on Computer Design
author list (cited authors)
Kumar, R., Bollapalli, K. C., Garg, R., Soni, T., & Khatri, S. P.
complete list of authors
Kumar, Rajesh||Bollapalli, Kalyana C||Garg, Rajesh||Soni, Tarun||Khatri, Sunil P