Design methodology for a 1.0 GHz microprocessor Conference Paper

abstract

• This paper describes the design methodology used to build an experimental 1.0 GigaHertz PowerPC integer microprocessor at IBM's Austin Research Laboratory. The high frequency requirements dictated the chip composition to be almost entirely custom macros using dynamic circuit techniques. The methodology presented will cover design and verification tools as well as circuit constraints and microarchitecture philosophy. The microarchitecture, circuits and tools were defined by the high frequency requirements of the processor as well as the aggressive design schedule and size of the design team.

name of conference

• Proceedings International Conference on Computer Design. VLSI in Computers and Processors (Cat. No.98CB36273)

authors

• Nowka, Kevin

published proceedings

• Proceedings - IEEE International Conference on Computer Design: VLSI in Computers and Processors
• Proceedings International Conference on Computer Design VLSI in Computers and Processors

author list (cited authors)

• Posluszny, S., Aoki, N., Boerstler, D., Burns, J., Dhong, S., Ghoshal, U., ... Vo, I.

citation count

• 29

complete list of authors

• Posluszny, S||Aoki, N||Boerstler, D||Burns, J||Dhong, S||Ghoshal, U||Hofstee, P||LaPotin, D||Lee, K||Meltzer, D||Ngo, H||Nowka, K||Silberman, J||Takahashi, O||Vo, I

publication date

• January 1998

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Conference on Computer Design - VLSI in Computers and Processors  Journal

keywords

• 33 Built Environment And Design
• 3303 Design
• 40 Engineering
• 4008 Electrical Engineering
• 4009 Electronics, Sensors And Digital Hardware
• 4010 Engineering Practice And Education

Digital Object Identifier (DOI)

• 10.1109/iccd.1998.727018

International Standard Book Number (ISBN) 10

• 0-8186-9099-2

start page

• 17

end page

• 23

URL

• http://dx.doi.org/10.1109/iccd.1998.727018