WaveSync: A low-latency source synchronous bypass network-on-chip architecture Conference Paper uri icon

abstract

  • WaveSync is a low-latency focused, network-on-chip architecture for globally-asynchronous locally-synchronous (GALS) designs. WaveSync facilitates low-latency communication leveraging the source-synchronous clock sent with the data, to time components in the downstream routers data-path to reduce the number of synchronizations needed. WaveSync accomplishes this by partitioning the router components at each node into different clock-domains, each synchronized with one of the the orthogonal incoming source synchronous clocks in a GALS 2D mesh network. The data and clock subsequently propagate through each node/router, synchronously, until the destination is reached, regardless of the number of hops it may take. As long as the data travel in the path of clock propagation, and no congestion is encountered, it will be propagated without latching, as if in a long-combinatorial path, with both the clock and the data accruing delay at the same rate. The result is that the need for synchronization between the mesochronous nodes and/or the asynchronous control associated with typical GALS network is completely eliminated. The proposed WaveSync network outperforms conventional GALS networks by 87-90% in average nanosecond latency with 1.8-6.5 times more throughput across synthetic traffic patterns and SPLASH-2 benchmark suite. © 2012 IEEE.

name of conference

  • 2012 IEEE 30th International Conference on Computer Design (ICCD 2012)

published proceedings

  • 2012 IEEE 30th International Conference on Computer Design (ICCD)

author list (cited authors)

  • Yang, Y. S., Kumar, R., Choi, G., & Gratz, P.

citation count

  • 6

complete list of authors

  • Yang, Yoon Seok||Kumar, Reeshav||Choi, Gwan||Gratz, Paul

publication date

  • September 2012

publisher