My research interests include fault-tolerance, verification simulation, high-performance VLSI circuits, radiation testing, design for dependability and software engineering.
Dash, R., Garg, R., Khatri, S. P., & Choi, G.
(2009).SEU Hardened Clock Regeneration Circuits. Proceedings - International Symposium on Quality Electronic Design, ISQED.
806-813.
Bhagawat, P., Dash, R., & Choi, G.
(2008).High Performance On the Fly Reconfigurable MIMO Detector. Conference record / Asilomar Conference on Signals, Systems & Computers. Asilomar Conference on Signals, Systems & Computers.
1849-1851.
Bhagawat, P., Wang, W., Uppal, M., Choi, G., Xiong, Z., Yeary, M., & Harris, A.
(2007).An FPGA Implementation of Dirty Paper Precoder. IEEE International Conference on Communications.
2761-2766.
Kim, E., Jayakumar, N., Bhagwat, P., Selvarathinam, A., Choi, G., & Khatri, S. P.
(2006).A high-speed fully-programmable VLSI decoder for regular LDPC codes. Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference).
3423-3426.
Gunnam, K. K., Choi, G. S., Wang, W., Kim, E., & Yeary, M. B.
(2006).Decoding of quasi-cyclic LDPC codes using an on-the-fly computation. Conference record / Asilomar Conference on Signals, Systems & Computers. Asilomar Conference on Signals, Systems & Computers.
1192-+.
Bhagawat, P., Uppal, M., & Choi, G.
(2005).Fpga Based Implementation of Decoder for Array Low-Density Parity-Check Codes. Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference).
v-29-v-32.
Singhal, R., Choi, G. S., & Mahapatra, R. N.
(2005).Quantized LDPC decoder design for binary symmetric channels. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
5782-5785.
Gunnam, K., Choi, G., & Yeary, M.
(2004).An LDPC Decoding Schedule for Memory Access Reduction. Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference).
v-173-v-176.