HR job title
- Associate Professor
- Contact Info
- 1 979 845 7486
- Websites
Choi, Gwan Associate Professor
Positions
- Associate Professor, Electrical and Computer Engineering, College of Engineering
My research interests include fault-tolerance, verification simulation, high-performance VLSI circuits, radiation testing, design for dependability and software engineering.
- Overview
- Publications
- Research
- Teaching
- Works By Students
- Background
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Overview
Publications
selected publications
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academic article
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Pourjabar, S., & Choi, G. S.
(2022).
A high-throughput multimode low-density parity-check decoder for 5G New Radio. 50(4), 1365-1374.
-
Pourjabar, S., & Choi, G. S.
(2021).
CVR: A Continuously Variable Rate LDPC Decoder Using Parity Check Extension for Minimum Latency. 93(8), 855-862.
-
Che, T., Xu, J., & Choi, G.
(2015).
Accelerated Dual-Path Asynchronous Circuit. IEEE Transactions on Circuits and Systems - II - Express Briefs.
62(9), 856-860.
-
Yang, Y. S., Kumar, R., Choi, G., & Gratz, P. V.
(2014).
WaveSync: Low-Latency Source-Synchronous Bypass Network-on-Chip Architecture. ACM Transactions on Design Automation of Electronic Systems.
19(4), 1-22.
-
Yang, Y. S., & Choi, G.
(2012).
Unequal Error Protection Based on DVFS for JSCD in Low-Power Portable Multimedia Systems. ACM Transactions on Embedded Computing Systems.
11(2), 30-21.
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Jain, T., Ramakrishna, M., Gratz, P. V., Sprintson, A., & Choi, G.
(2011).
Asynchronous Bypass Channels for Multi-Synchronous NoCs: A Router Microarchitecture, Topology, and Routing Algorithm. 30(11), 1663-1676.
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Lee, S. E., Yang, Y. S., Choi, G. S., Wu, W., & Iyer, R.
(2011).
Low-Power, Resilient Interconnection with Orthogonal Latin Squares. IEEE Design and Test of Computers.
28(2), 30-38.
-
Garg, R., Jayakumar, N., Khatri, S. P., & Choi, G. S.
(2009).
Circuit-Level Design Approaches for Radiation-Hard Digital Electronics. 17(6), 781-792.
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Abbott, B., Abdesselam, A., Abolins, M., Abramov, V., Acharya, B. S., Adams, D. L., ... Zylberstejn, A.
(2001).
Quasi-model-independent search for new high p(T) physics at D0. Physical Review Letters.
86(17), 3712-3717.
-
Abbott, B., Abolins, M., Abramov, V., Acharya, B. S., Adams, D. L., Adams, M., ... Zylberstejn, A.
(2001).
Search for large extra dimensions in dielectron and diphoton production. Physical Review Letters.
86(7), 1156-1161.
-
Hwang, S. H., & Choi, G. S.
(2000).
A reliability testing environment for off-the-shelf memory subsystems. IEEE Design and Test of Computers.
17(3), 116-124.
-
Min, B., & Choi, G.
(2000).
Verification Simulation Acceleration Using Code-Perturbation. Journal of Electronic Testing.
16(1-2), 83-90.
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Cha, H. S., Rudnick, E. M., Patel, J. H., Iyer, R. K., & Choi, G. S.
(1996).
A gate-level simulation environment for alpha-particle-induced transient faults. IEEE Transactions on Computers.
45(11), 1248-1256.
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Choi, G. S., Iyer, R. K., & Carreno, V. A.
(1990).
Simulated fault injection: a methodology to evaluate fault tolerant microprocessor architectures. 39(4), 486-491.
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Pourjabar, S., & Choi, G. S.
(2022).
A high-throughput multimode low-density parity-check decoder for 5G New Radio. 50(4), 1365-1374.
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book
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Rahman, M., & Choi, G. S.
(2017).
K-Best Decoders for 5G+ Wireless Communication. Springer Nature.
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Rahman, M., & Choi, G. S.
(2017).
K-Best Decoders for 5G+ Wireless Communication. Springer Nature.
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conference paper
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Che, T., Xu, J., & Choi, G.
(2016).
Overlapped List Successive Cancellation Approach for Hardware Efficient Polar Code Decoder. IEEE International Symposium on Circuits and Systems.
2463-2466.
-
Che, T., Xu, J., & Choi, G.
(2016).
TC: Throughput Centric Successive Cancellation Decoder Hardware Implementation for Polar Codes. Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference).
991-995.
-
Rahman, M., Rohani, E., & Choi, G. S.
(2015).
An Iterative LR-Aided MMSE Extended Soft MIMO Decoding Algorithm. 889-894.
-
Xu, J., & Choi, G.
(2015).
Compressive Sensing and Reception for MIMO-OFDM Based Cognitive Radio. 884-888.
-
Rohani, E., Xu, J., Che, T., Rahman, M., Choi, G., & Lu, M. i.
(2014).
Asynchronous Baseband Processor Design for Cooperative MIMO Satellite Communication. The ... Midwest Symposium on Circuits and Systems conference proceedings : MWSCAS. Midwest Symposium on Circuits and Systems.
833-836.
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Rohani, E., Xu, J., Choi, G., & Lu, M. i.
(2014).
Low-Power On-the-Fly Reconfigurable Iterative MIMO Detection and LDPC Decoding Design. Applied Mechanics and Materials.
1825-1829.
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Rahman, M., Rohani, E., & Choi, G. S.
(2014).
An Iterative Soft Decision Based Adaptive K-best Decoder without SNR Estimation. Conference record / Asilomar Conference on Signals, Systems & Computers. Asilomar Conference on Signals, Systems & Computers.
1016-1020.
-
Xu, J., Che, T., Rohani, E., & Choi, G.
(2014).
Asynchronous Design for Precision-Scaleable Energy-Efficient LDPC Decoder. Conference record / Asilomar Conference on Signals, Systems & Computers. Asilomar Conference on Signals, Systems & Computers.
136-140.
-
Park, P., Choi, G. S., Rohani, E., & Song, I.
(2014).
Optimization of thermoelectric system for pavement energy harvesting. 1827-1838.
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Xu, J., Rohani, E., Rahman, M., & Choi, G.
(2014).
Signal Reconstruction Processor Design For Compressive Sensing. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
2539-2542.
-
Xu, J., Che, T., & Choi, G.
(2014).
XJ-BP: Express Journey Belief Propagation Decoding for Polar Codes. 1-6.
-
Yu, S., Li, P., Lin, H., Rohani, E., Choi, G., Shao, B., & Wang, Q.
(2013).
Support Vector Machine Based Detection of Drowsiness Using Minimum EEG Features. 827-835.
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Kumar, R., Deshpande, H., Choi, G., Sprintson, A., & Gratz, P.
(2013).
Bidirectional Interconnect Design for Low Latency High Bandwidth NoC. 215-218.
-
Yang, Y. S., Taylor, A., & Choi, G.
(2013).
Data Processing Logic for Stacked Wafer-Scale CMOS Radiation Sensor Network. IEEE Nuclear Science Symposium conference record. Nuclear Science Symposium.
1-8.
-
Yang, Y. S., Deshpande, H., Choi, G., & Gratz, P.
(2012).
Exploiting Path Diversity for Low-Latency and High-Bandwidth with the Dual-path NoC Router. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
2433-2436.
-
Yang, Y. S., Kumar, R., Choi, G., & Gratz, P.
(2012).
WaveSync: A Low-Latency Source Synchronous Bypass Network-On-Chip Architecture. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
241-248.
-
Yang, Y. S., Bhagawat, P., & Choi, G.
(2011).
Energy-efficient MIMO detection using unequal error protection for embedded joint decoding system. Design Automation Conference.
579-584.
-
Kumar, R., Yang, Y. S., & Choi, G.
(2011).
Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs. Proceedings of the IEEE International Conference on VLSI Design.
238-243.
-
Yang, Y. S., & Choi, G.
(2010).
Low-Power Baseband Processing for Wireless Multimedia Systems using Unequal Error Protection. 1-6.
-
Yang, Y. S., & Choi, G.
(2010).
Low-Power Embedded LDPC-H.264 Joint Decoding Architecture Based on Unequal Error Protection. 1-6.
-
Jain, T., Gratz, P. V., Sprintson, A., & Choi, G.
(2010).
Asynchronous Bypass Channels: Improving Performance for Multi-Synchronous NoCs. 51-58.
-
Bhagawat, P., Dash, R., & Choi, G.
(2009).
Systolic like soft-detection architecture for 4x4 64-QAM MIMO system. Proceedings -Design, Automation and Test in Europe, DATE.
870-873.
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Dash, R., Garg, R., Khatri, S. P., & Choi, G.
(2009).
SEU Hardened Clock Regeneration Circuits. Proceedings - International Symposium on Quality Electronic Design, ISQED.
806-813.
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Bhagawat, P., Dash, R., & Choi, G.
(2009).
Array Like Runtime Reconfigurable MIMO Detectors for 802.11n WLAN: A Design Case Study. 751-756.
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Wang, W., Kim, E., Gunnam, K. K., & Choi, G. S.
(2009).
Low-Power VLSI Design of LDPC Decoder Using Dynamic Voltage and Frequency Scaling for Additive White Gaussian Noise Channels. Journal of Low Power Electronics.
303-312.
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Gunnam, K. K., Choi, G. S., Yeary, M. B., Yang, S., & Lee, Y.
(2008).
Next Generation Iterative LDPC Solutions for Magnetic Recording Storage. Conference record / Asilomar Conference on Signals, Systems & Computers. Asilomar Conference on Signals, Systems & Computers.
1148-+.
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Singhal, R., Choi, G., & Mahapatra, R. N.
(2008).
Data Handling Limits of On-Chip Interconnects. IEEE Transactions on Very Large Scale Integration Systems.
707-713.
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Bhagawat, P., Dash, R., & Choi, G.
(2008).
Architecture for Reconfigurable MIMO Detector and its FPGA Implementation. 61-64.
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Bhagawat, P., Dash, R., & Choi, G.
(2008).
High Performance On the Fly Reconfigurable MIMO Detector. Conference record / Asilomar Conference on Signals, Systems & Computers. Asilomar Conference on Signals, Systems & Computers.
1849-1851.
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Gunnam, K. K., Choi, G. S., Yeary, M. B., & Atiquzzaman, M.
(2007).
VLSI architectures for layered decoding for irregular LDPC codes of WiMax. 2013 National Conference on Communications, NCC 2013.
4542-+.
-
Gunnam, K., Choi, G., Yeary, M., & Zhai, Y.
(2007).
A Low-Power Preamble Detection Methodology for Packet Based RF Modems on All-Digital Sensor Front-Ends. IEEE Instrumentation and Measurement Technology Conference Proceedings.
1-4.
-
Bhagawat, P., Wang, W., Uppal, M., Choi, G., Xiong, Z., Yeary, M., & Harris, A.
(2007).
An FPGA Implementation of Dirty Paper Precoder. IEEE International Conference on Communications.
2761-2766.
-
Chang, S., & Choi, G.
(2007).
Gate-Level Exception Handling Design for Noise Reduction in High-Speed VLSI Circuits. Proceedings of the IEEE International Conference on VLSI Design.
1-6.
-
Wang, W., & Choi, G.
(2007).
Minimum-Energy LDPC Decoder for Real-Time Mobile Application. Proceedings -Design, Automation and Test in Europe, DATE.
343-348.
-
Gunnam, K., Choi, G., Wang, W., & Yeary, M.
(2007).
Multi-Rate Layered Decoder Architecture for Block LDPC Codes of the IEEE 802.11n Wireless Standard. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
1645-1648.
-
Wang, W., & Choi, G.
(2007).
Speculative Energy Scheduling for LDPC Decoding. 1-6.
-
Gunnam, K., Wang, W., Choi, G., & Yeary, M.
(2007).
VLSI Architectures for Turbo Decoding Message Passing Using Min-Sum for Rate-Compatible Array LDPC Codes. 561-566.
-
Gunnam, K. K., Choi, G. S., & Yeary, M. B.
(2007).
A parallel VLSI architecture for layered decoding for array LDPC codes. Proceedings of the IEEE International Conference on VLSI Design.
738-+.
-
Bhagawat, P., Ekambavanan, S., Das, S., Choi, G., & Khatri, S. P.
(2007).
VLSI implementation of a staggered sphere decoder design for MIMO detection. 228-235.
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Kim, E., Jayakumar, N., Bhagwat, P., Selvarathinam, A., Choi, G., & Khatri, S. P.
(2006).
A high-speed fully-programmable VLSI decoder for regular LDPC codes. Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference).
3423-3426.
-
Gunnam, K. K., Choi, G. S., Wang, W., Kim, E., & Yeary, M. B.
(2006).
Decoding of quasi-cyclic LDPC codes using an on-the-fly computation. Conference record / Asilomar Conference on Signals, Systems & Computers. Asilomar Conference on Signals, Systems & Computers.
1192-+.
-
Garg, R., Jayakumar, N., Khatri, S. P., & Choi, G.
(2006).
A design approach for radiation-hard digital electronics. Design Automation Conference.
773-778.
-
Singhal, R., Choi, G., & Mahapatra, R.
(2006).
Information Theoretic Approach to Address Delay and Reliability in Long On-Chip Interconnects. IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers.
310-314.
-
Singhal, R., Choi, G. S., & Mahapatra, R.
(2006).
Information theoretic capacity of long on-chip interconnects in the presence of crosstalk. Proceedings - International Symposium on Quality Electronic Design, ISQED.
407-+.
-
Singhal, R., Choi, G., & Mahapatra, R. N.
(2006).
Programmable LDPC Decoder Based on the Bubble-Sort Algorithm. Proceedings of the IEEE International Conference on VLSI Design.
1-6.
-
Chang, S., & Choi, G.
(2006).
Timing Failure Analysis of Commercial CPUs Under Operating Stress. Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
245-253.
-
Kim, E., & Choi, G. S.
(2005).
Diagonal Low-Density Parity-Check code for simplified routing in decoder. IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation.
756-761.
-
Bhagawat, P., Uppal, M., & Choi, G.
(2005).
Fpga Based Implementation of Decoder for Array Low-Density Parity-Check Codes. Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference).
v-29-v-32.
-
Selvarathinam, A., & Choi, G.
(2005).
Tiling Parity-Check Matrix for Reduced Complexity High Throughput Low-Density Parity-Check Decoders. IEEE Workshop on Signal Processing Systems, SiPS: Design and Implementation.
744-749.
-
Kim, E., & Choi, G. S.
(2005).
LDPC code for reduced routing decoder. 991-994.
-
Singhal, R., Choi, G. S., & Mahapatra, R. N.
(2005).
Quantized LDPC decoder design for binary symmetric channels. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
5782-5785.
-
Tayade, R., & Choi, G.
(2004).
Fast simulation technique for LDPC code analysis. 707-713.
-
Singhal, R., Choi, G. S., Mickler, N., & Koteeswaran, P.
(2004).
Scaleable check node centric architecture for LDPC decoder. IEEE International Symposium on Circuits and Systems.
189-192.
-
Gunnam, K., Choi, G., & Yeary, M.
(2004).
An LDPC Decoding Schedule for Memory Access Reduction. Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference).
v-173-v-176.
-
Selvarathinam, A., Choi, G., Narayanan, K., Prabhakar, A., & Kim, E.
(2003).
A massively scaleable decoder architecture for low-density parity-check codes. IEEE International Symposium on Circuits and Systems.
61-64.
-
Selvarathinam, A., Kim, E., & Choi, G.
(2003).
Low-density parity-check decoder architecture for high throughput optical fiber channels. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
520-525.
-
Min, B., & Choi, G.
(2001).
ECC: Extended Condition Coverage for Design Verification Using Excitation and Observation*. Proceedings of IEEE Pacific Rim International Symposium on Dependable Computing, PRDC.
183-190.
-
Min, B., & Choi, G.
(2001).
RTL Functional Verification Using Excitation and Observation Coverage. Proceedings - IEEE International High-Level Design Validation and Test Workshop, HLDVT.
58-63.
-
Yang, Z., Min, B., & Choi, G.
(2001).
Simulation using code-perturbation: Black- and white-box approach. Proceedings - International Symposium on Quality Electronic Design, ISQED.
44-49.
-
Yang, Z., Min, B. Y., & Choi, G.
(2000).
Si-emulation: System verification using simulation and emulation. International Test Conference.
160-169.
-
Ries, G. L., Choi, G. S., & Iyer, R. K.
(1994).
Device-level transient fault modeling. Ftcs.
86-94.
-
Cha, H., Rudnick, E. M., Choi, G. S., Patel, J. H., & Iyer, R. K.
(1993).
A fast and accurate gate-level transient fault simulation environment. Ftcs.
310-319.
-
Choi, G. S., Iyer, R. K., & Saab, D. G.
(1993).
Fault behavior dictionary for simulation of device-level transients. 6-9.
-
Choi, G. S., & Iyer, R. K.
(1993).
Wear-out simulation environment for VLSI designs. Ftcs.
320-329.
-
Choi, G., Iyer, R., & Carreno, V.
(1989).
FOCUS: an experimental environment for validation of fault-tolerant systems-case study of a jet-engine controller. 561-564.
-
Che, T., Xu, J., & Choi, G.
(2016).
Overlapped List Successive Cancellation Approach for Hardware Efficient Polar Code Decoder. IEEE International Symposium on Circuits and Systems.
2463-2466.
-
institutional repository document
-
Pourjabar, S., & Choi, G. S.
(2021).
A High-Throughput Multi-Mode LDPC Decoder for 5G NR
-
Pourjabar, S., & Choi, G. S.
(2021).
A High-Throughput Multi-Mode LDPC Decoder for 5G NR
-
patent
-
Gunnam, K. K., & Choi, G. S.
(2021).
Low density parity check decoder
-
Gunnam, K. K., & Choi, G. S.
(2020).
Low density parity check decoder
-
Gunnam, K. K., & Choi, G. S.
(2018).
Low density parity check decoder
-
Gunnam, K., & Choi, G.
(2015).
Low density parity check decoder
-
Gunnam, K. K., & Choi, G. S.
(2015).
Low density parity check decoder
-
Gunnam, K., & Choi, G.
(2014).
Low density parity check decoder for regular LDPC codes
-
Gunnam, K., & Choi, G.
(2013).
Low density parity check decoder for irregular LDPC codes
-
Gunnam, K., & Choi, G.
(2013).
Low density parity check decoder for irregular LDPC codes
-
Gunnam, K., & Choi, G.
(2013).
Low density parity check decoder for regular LDPC codes
-
Gunnam, K. K., & Choi, G. S.
(2021).
Low density parity check decoder
Research
co-principal investigator on
Teaching
teaching activities
- ECEN248 Intro To Dgtl Sym Dsgn Instructor
- ECEN454 Dig Integratedckt Des Instructor
- ECEN475 Intro Vlsi Sysm Design Instructor
- ECEN491 Hnr-research Instructor
- ECEN654 Vlsi Systems Design Instructor
- ECEN684 Professional Internship Instructor
- ECEN684 Professional Internship Instructor
- ECEN689 Sptp: Digital Inte Circuit Des Instructor
- ECEN691 Research Instructor
- ECEN714 Digital Integrated Circuit Des Instructor
Works By Students
chaired theses and dissertations
-
Arya, Richeek (2012-10). Soft MIMO Detection on Graphics Processing Units and Performance Study of Iterative MIMO Decoding.
-
Bhagawat, Pankaj (2012-02). Hardware Accelerator for MIMO Wireless Systems.
-
Chang, Sanghoan (2009-05). Empirical timing analysis of CPUs and delay fault tolerant design using partial redundancy.
-
Dash, Rajballav (2009-12). VLSI Implementation of Low Power Reconfigurable MIMO Detector.
-
Deshpande, Hrishikesh (2012-07). Multipath Router Architectures to Reduce Latency in Network-on-Chips.
-
Gao, Di (2015-11). Multi-harmonic Modeling of Low-power PWM DC-DC Converter.
-
Gunnam, Kiran Kumar (2009-05). Area and energy efficient VLSI architectures for low-density parity-check decoders using an on-the-fly computation.
-
Kumar, Poornachandran (2011-10). Efficient Lookahead Routing and Header Compression For Multicasting in Networks-On-Chip.
-
Kumar, Reeshav (2012-10). Communication Reliability in Network on Chip Designs.
-
Okorafor, Ekpe Apia (2007-04). Design and analysis of a 3-dimensional cluster multicomputer architecture using optical interconnection for petaFLOP computing.
-
Pu, Lingjun (2015-08). A Software Defined Radio Experimental Platform for GPS/GNSS Signal Reception Analysis.
-
Selvarathinam, Anand Manivannan (2005-11). High throughput low power decoder architectures for low density parity check codes.
-
Singhal, Rohit (2007-09). Data integrity for on-chip interconnects.
-
Tamilarasan, Karthik Prabhu (2012-02). Built-In Self Test (BIST) for Realistic Delay Defects.
-
Vageesan, Gopinath (2007-04). On improving performance and conserving power in cluster-based web servers.
-
Wang, Qian (2016-08). Architectures and Design of VLSI Machine Learning Systems.
-
Wang, Weihuang (2009-05). Low power low-density parity-checking (ldpc) codes decoder design using dynamic voltage and frequency scaling.
-
Yu, Shaoda (2014-08). EEG-based Drowsiness Detection using Support Vector Machine.
Background
education and training
- Ph.D. in Electrical and Computer Engineering, University of Illinois at Urbana Champaign - (Urbana, Illinois, United States) 1994
awards and honors
Contact
first name
- Gwan
has last name
- Choi
mailing address
-
Texas A&M University
Electrical Engineering
3128 TAMU
College Station, TX 77843-3259
USA
Other
- gwanchoi@tamu.edu