High Performance On the Fly Reconfigurable MIMO Detector Conference Paper

abstract

• Upcoming wireless communication standards such as 802.11n, WiMax etc require support for multiple modulation schemes. These standards all have multiple transmit and receive antennas(MIMO). Hence, the MIMO detector hardware should be able to accommodate different modulation schemes preferably on a single reconfigurable architecture. This paper presents an high performance FPGA implementation of a novel MIMO detector architecture that is able to reconfigure on the fly and provides quasi-optimal Bit Error Rate(BER). The design is implemented in Xilinx Virtex-4, and achieves a sustained throughput of 1.72Gbps for QPSK, 860Mbps for 16-QAM, and 430Mbps for 64-QAM. The total area is approximately 140.26KGates equivalent. 2008 IEEE.

name of conference

• 2008 42nd Asilomar Conference on Signals, Systems and Computers

authors

• Choi, Gwan

published proceedings

• 2008 42nd Asilomar Conference on Signals, Systems and Computers

author list (cited authors)

• Bhagawat, P., Dash, R., & Choi, G.

citation count

• 0

complete list of authors

• Bhagawat, Pankaj||Dash, Rajballav||Choi, Gwan

publication date

• January 2008

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Conference record / Asilomar Conference on Signals, Systems & Computers. Asilomar Conference on Signals, Systems & Computers  Journal

Digital Object Identifier (DOI)

• 10.1109/acssc.2008.5074748

International Standard Book Number (ISBN) 13

• 9781424429417

start page

• 1849

end page

• 1851

URL

• http://dx.doi.org/10.1109/acssc.2008.5074748