A high-speed fully-programmable VLSI decoder for regular LDPC codes Conference Paper uri icon

abstract

  • This paper presents a VLSI implementation of a Low-Density Parity Check (LDPC) decoder that achieves 2.4 Gbps throughput yet permits real-time configuration of (1) rate, (2) code length, and (3) the parity equations. This decoder can be programmed in the field, much like an FPGA. We describe the architectural, circuit-level and layout-level details of our implementation. Our design can handle variable rate codes of length up to 1024, and is implemented in a 0.1 m VLSI fabrication process. Our design has a die size of 12mm by 8mm and a power consumption of 7W. This implementation can extended to handle longer codes in a partially parallel manner, and allow for on-the-fly modification of the code. 2006 IEEE.

published proceedings

  • 2006 IEEE INTERNATIONAL CONFERENCE ON ACOUSTICS, SPEECH AND SIGNAL PROCESSING, VOLS 1-13

author list (cited authors)

  • Kim, E., Jayakumar, N., Bhagwat, P., Selvarathinam, A., Choi, G., & Khatri, S. P.

complete list of authors

  • Kim, Euncheol||Jayakumar, Nikhil||Bhagwat, Pankaj||Selvarathinam, Anand||Choi, Gwan||Khatri, Sunil P

publication date

  • December 2006