Information theoretic capacity of long on-chip interconnects in the presence of crosstalk Conference Paper

abstract

• This paper presents a framework for calculating the data capacity of long on chip interconnects. This framework is based on the Shannon's capacity theorem. The extension of this theorem into binary symmetric channels (BSC) is studied and applied to the VLSI interconnects. This paper presents a simulation study that shows the variation of capacity with a variety physical and operating conditions of long wires. The results show that the operating frequency, that was arrived at using a worst case delay analysis, can be vastly increased through use of error correction coding. This capacity can also be used as a benchmark for evaluation of coding schemes on interconnects. 2006 IEEE.

name of conference

• 7th International Symposium on Quality Electronic Design (ISQED'06)

authors

• Choi, Gwan
• Mahapatra, Rabinarayan

published proceedings

• ISQED 2006: PROCEEDINGS OF THE 7TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN

author list (cited authors)

• Singhal, R., Choi, G. S., & Mahapatra, R.

citation count

• 6

complete list of authors

• Singhal, Rohit||Choi, Gwan S||Mahapatra, Rabi

publication date

• January 2006

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings - International Symposium on Quality Electronic Design, ISQED  Journal

keywords

• Genetics

Digital Object Identifier (DOI)

• 10.1109/isqed.2006.76

International Standard Book Number (ISBN) 10

• 0-7695-2523-7

International Standard Book Number (ISBN) 13

• 9780769525235

start page

• 407

end page

• +

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fisqed.2006.76