publication venue for
- Joint-optimization of Node Placement and UAV's Trajectory for Self-sustaining Air-Ground IoT system 2022
- Transaction Level Stimulus Optimization in Functional Verification Using Machine Learning Predictors 2022
- Fast Mapping-Based High-Level Synthesis of Pipelined Circuits 2019
- MReC: A Multilayer Photonic Reservoir Computing Architecture 2019
- Dot-Product Engine as Computing Memory to Accelerate Machine Learning Algorithms 2016
- A 2-Layer Laser Multiplexed Photonic Network-on-Chip 2015
- A 2-Layer Laser Multiplexed Photonic Network-on-Chip 2015
- An Enlarged-Partition Based Preconditioned Iterative Solver for Parallel Power Grid Simulation 2015
- Temperature Aware Energy Management or Real-Time Scheduling 2011
- Transient and Fine-Grained Voltage Adaptation for Variation Resilience in VLSI Interconnects 2011
- A Dual-Level Adaptive Supply Voltage System for Variation Resilience 2010
- Useful Clock Skew Optimization under A Multi-corner Multi-mode Design Framework 2010
- Design and Implementation of a Sub-threshold BFSK Transmitter 2009
- SEU Hardened Clock Regeneration Circuits 2009
- The Impact of BEOL Lithography Effects on the SRAM Cell Performance and Yield 2009
- An efficient alorintham for RLC buffer insertion 2007
- Information theoretic capacity of long on-chip interconnects in the presence of crosstalk 2006
- An improved AMG-based method for fast power grid analysis 2006
- Core Network Interface Architecture and Latency Constrained On-Chip This work was supported by NSF award, CNS-0509483. 2006
- Efficient model update for general link-insertion networks 2006
- Power Gating with Multiple Sleep Modes 2006
- SRAM Local Bit Line Access Failure Analyses 2006
- Controlled-load limited switch dynamic logic circuit 2005
- Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization 2005
- Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization 2005
- Simulation using code-perturbation: Black- and white-box approach 2001