Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization Conference Paper uri icon


  • Parametric yield loss has become a serious concern in leakage dominated technologies. We discuss the impact of leakage on parametric yield and show that leakage can cause yield windows to shrink by imposing a two-sided constraint on the window. We present a mathematical framework for yield estimation under device process variation for given power and frequency constraints. The model is validated against Monte Carlo simulations for an industry process and is shown to have typical error of less than 5%. We then demonstrate the importance of optimal supply voltage selection for yield maximization. We also investigate the sensitivity of parametric yield to applied frequency and power constraints. Finally, we apply the proposed framework to the problem of maximizing the shipping frequency in the presence of given yield and power constraints. 2005 IEEE.

name of conference

  • Sixth International Symposium on Quality of Electronic Design (ISQED'05)

published proceedings

  • Sixth International Symposium on Quality of Electronic Design (ISQED'05)

author list (cited authors)

  • Rao, R., Agarwal, K., Devgan, A., Nowka, K., Sylvester, D., & Brown, R.

citation count

  • 16

complete list of authors

  • Rao, Rahul||Agarwal, Kanak||Devgan, Anirudh||Nowka, Kevin||Sylvester, Dennis||Brown, Richard

publication date

  • January 2005