Controlled-load limited switch dynamic logic circuit Conference Paper

abstract

• Limited switch dynamic logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounce. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated. 2005 IEEE.

name of conference

• Sixth International Symposium on Quality of Electronic Design (ISQED'05)

authors

• Nowka, Kevin

published proceedings

• 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS

author list (cited authors)

• Sivagnaname, J., Ngo, H. C., Nowka, K. J., Montoye, R. K., & Brown, R. B.

citation count

• 0

complete list of authors

• Sivagnaname, J||Ngo, HC||Nowka, KJ||Montoye, RK||Brown, RB

publication date

• January 2005

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings - International Symposium on Quality Electronic Design, ISQED  Journal

keywords

• 34 Chemical Sciences
• 3403 Macromolecular And Materials Chemistry
• 40 Engineering

Digital Object Identifier (DOI)

• 10.1109/ISQED.2005.35

International Standard Book Number (ISBN) 10

• 0-7695-2301-3

International Standard Book Number (ISBN) 13

• 9780769523019

start page

• 83

end page

• 87

URL

• http://dx.doi.org/10.1109/isqed.2005.35