Controlled-load limited switch dynamic logic circuit Conference Paper uri icon

abstract

  • Limited switch dynamic logic (LSDL), a high performance logic circuit, has been modified by introducing a pseudo-nMOS style load. The resultant circuit consumes less power, primarily due to the reduction of capacitance on the clock network. The controlled-load LSDL is shown to be more robust to noise and power rail bounce. A 64-bit rotator circuit was used in the analysis. The effect of process variation on circuit performance is also evaluated. 2005 IEEE.

name of conference

  • Sixth International Symposium on Quality of Electronic Design (ISQED'05)

published proceedings

  • 6TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, PROCEEDINGS

author list (cited authors)

  • Sivagnaname, J., Ngo, H. C., Nowka, K. J., Montoye, R. K., & Brown, R. B.

citation count

  • 0

complete list of authors

  • Sivagnaname, J||Ngo, HC||Nowka, KJ||Montoye, RK||Brown, RB

publication date

  • January 2005