Core Network Interface Architecture and Latency Constrained On-Chip This work was supported by NSF award, CNS-0509483. Conference Paper uri icon


  • This paper proposes a core network interface (CNI) architecture to interface IP cores with on-chip networks. Besides the basic functionality of packetizing communication requests and responses, we expect the CNI to provide additional services critical to communication in complex systems-on-a-chip (SoC). A CNI for interfacing with OCP-compliant core interfaces was developed for architecture validation. With the support of a modified on-chip router, the CNI was setup to bound on-chip communication latency jitter. We observed that jitter due to inefficient virtual channel allocation in a particular configuration of an on-chip interconnection network lead to latency variations of up to 400%. Using a class-based virtual channel allocation scheme in a 2D torus network, we provide for predictable end-to-end latency. While the proposed scheme does not guarantee least possible end-to-end latency, it provides for constrained bounds. 2006 IEEE.

name of conference

  • 7th International Symposium on Quality Electronic Design (ISQED'06)

published proceedings

  • 7th International Symposium on Quality Electronic Design (ISQED'06)

author list (cited authors)

  • Bhojwani, P., & Mahapatra, R. N.

citation count

  • 11

complete list of authors

  • Bhojwani, Praveen||Mahapatra, Rabi N

publication date

  • January 2006