Design and Implementation of a Sub-threshold BFSK Transmitter Conference Paper uri icon

abstract

  • Power Consumption in VLSI circuits is currently a major issue in the semiconductor industry. Power is a first order design constraint in many applications. However, a growing class of applications need extreme low power but do not need high speed. Sub-threshold circuit design can be used for these applications. Unfortunately, sub-threshold circuits exhibit an exponential sensitivity to process, voltage and temperature (PVT) variations. In this paper we implement and test a robust subthreshold design flow which uses circuit level PVT compensation to stabilize circuit performance. We design and fabricate a subthreshold BFSK transmitter chip. The transmitter is specified to transmit baseband signals up to a data rate of 32kbps. Experiments using the fabricated die, verify the functionality of the design show that the sub-threshold circuit consumes 19.4x lower power than the traditional standard cell based implementation on the same die. 2009 IEEE.

name of conference

  • 2009 10th International Symposium on Quality of Electronic Design

published proceedings

  • ISQED 2009: PROCEEDINGS 10TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN, VOLS 1 AND 2

author list (cited authors)

  • Paul, S., Garg, R., Khatri, S. P., & Vaidya, S.

citation count

  • 4

complete list of authors

  • Paul, Suganth||Garg, Rajesh||Khatri, Sunil P||Vaidya, Sheila

publication date

  • March 2009