Efficient Model Update for General Link-Insertion Networks Conference Paper uri icon


  • Link insertion has been proposed as a means of incremental design to improve performance robustness of linear passive networks. In clock network design, links can be inserted between subnetworks to reduce the variability of clock skews introduced by process and environmental fluctuations, thereby improving the network's immunity to PVT variations. Under these scenarios, it is desired to incrementally compute a reduced-order model for the updated network in order to efficiently evaluate the effectiveness of link insertions. In this paper, we present an efficient model update scheme for general link-insertion networks. By updating the Krylov projection subspace used in model order reduction, the proposed scheme can efficiently compute a reduced-order model for the network with inserted links. More generally, we extend the proposed approach to consider the merging of a (small) multiple-input linear network with a much larger network. We demonstrate the usage of the proposed technique for clock networks and general RLC circuits with an arbitrary number of link insertions as well as the more general case where the inserted links are in the form of a linear network. 2006 IEEE.

name of conference

  • 7th International Symposium on Quality Electronic Design (ISQED'06)

published proceedings

  • 7th International Symposium on Quality Electronic Design (ISQED'06)

author list (cited authors)

  • Zhuo Feng, .., Peng Li, .., & Jiang Hu.

citation count

  • 3

publication date

  • January 2006