VLSI architectures for layered decoding for irregular LDPC codes of WiMax Conference Paper

abstract

• We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. The decoder has the following advantages: 55% savings in memory, reduction of routers by 50%, and increase of throughput by 2x when compared to the recent state-of-the-art decoder architectures. 2007 IEEE.

name of conference

• 2007 IEEE International Conference on Communications

authors

• Choi, Gwan

published proceedings

• 2007 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-14

author list (cited authors)

• Gunnam, K. K., Choi, G. S., Yeary, M. B., & Atiquzzaman, M.

citation count

• 63

complete list of authors

• Gunnam, Kiran K||Choi, Gwan S||Yeary, Mark B||Atiquzzaman, Mohammed

publication date

• June 2007

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• 2013 National Conference on Communications, NCC 2013  Journal

keywords

• Decoder Architecture
• Ieee 802.16e
• Irregular Ldpc
• Layered Decoding
• Low-density Parity-check (ldpc) Codes
• Offset Min-sum
• On-the-fly Computation
• Turbo-decoding Message Passing

Digital Object Identifier (DOI)

• 10.1109/ICC.2007.750

International Standard Book Number (ISBN) 10

• 1424403537

International Standard Book Number (ISBN) 13

• 978-1-4244-0352-3

start page

• 4542

end page

• +

URL

• http://dx.doi.org/10.1109/icc.2007.750