VLSI architectures for layered decoding for irregular LDPC codes of WiMax Conference Paper uri icon

abstract

  • We present a new multi-rate architecture for decoding irregular LDPC codes in IEEE 802.16e WiMax standard. The proposed architecture utilizes the value-reuse property of offset min-sum, block-serial scheduling of computations and turbo decoding message passing algorithm. The decoder has the following advantages: 55% savings in memory, reduction of routers by 50%, and increase of throughput by 2x when compared to the recent state-of-the-art decoder architectures. 2007 IEEE.

name of conference

  • 2007 IEEE International Conference on Communications

published proceedings

  • 2007 IEEE INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1-14

author list (cited authors)

  • Gunnam, K. K., Choi, G. S., Yeary, M. B., & Atiquzzaman, M.

citation count

  • 63

complete list of authors

  • Gunnam, Kiran K||Choi, Gwan S||Yeary, Mark B||Atiquzzaman, Mohammed

publication date

  • January 1, 2007 11:11 AM