An FPGA Implementation of Dirty Paper Precoder Conference Paper uri icon

abstract

  • Dirty paper code (DPC) can be used in a number of communication network applications; broadcast channels, multiuser interference channels and ISI channels to name a few. We study various implementation bottlenecks and issues with implementing a DPC pre-coder based on nested trellis technique. The aim is to achieve a practical hardware realization of the precoder for wireless LAN/DSL applications. We describe the architectural development process and realization of the precoder on a Xilinx Virtex 2V8000 FPGA. To the best of our knowledge this is the first reported DPC pre-coder hardware implementation. ©2007 IEEE.

name of conference

  • 2007 IEEE International Conference on Communications

published proceedings

  • 2007 IEEE International Conference on Communications

author list (cited authors)

  • Bhagawat, P., Wang, W., Uppal, M., Choi, G., Xiong, Z., Yeary, M., & Harris, A.

citation count

  • 9

complete list of authors

  • Bhagawat, P||Wang, W||Uppal, M||Choi, G||Xiong, Z||Yeary, M||Harris, A

publication date

  • June 2007

publisher