VLSI Architectures for Turbo Decoding Message Passing Using Min-Sum for Rate-Compatible Array LDPC Codes Conference Paper uri icon

abstract

  • In the recent literature, turbo decoding message passing (TDMP) or layered decoding has been proposed for the decoding of low-density parity-check (LDPC) codes using a trellis-based BCJR algorithm in check node units (CNU). We present a new architecture for supporting rate compatible array LDPC codes that uses an offset-based min-sum decoding algorithm instead of the BCJR. The proposed architecture utilizes the value-reuse properties of min-sum and block-serial scheduling of computations, along with TDMP. This novel architecture has the following features: removal of memory needed to store the sum of the variable node messages and the channel values, removal of memory needed to store the variable node messages, 40%-72% savings in storage of extrinsic messages depending on rate of the codes, reduction of routers by 50%, and increase of throughput up to 2x. Implementations on our test-bed FPGA achieve decoded throughputs up to 1.36 Gbps and 2.27 Gbps for each iteration for (5,k) and (3,k) array LDPC codes, respectively. ASIC implementation achieve decoded throughputs up to 5.9 Gbps for each iteration for (5,k) array LDPC codes. 2007 IEEE.

name of conference

  • 2007 2nd International Symposium on Wireless Pervasive Computing

published proceedings

  • 2007 2nd International Symposium on Wireless Pervasive Computing

author list (cited authors)

  • Gunnam, K., Wang, W., Choi, G., & Yeary, M.

citation count

  • 0

complete list of authors

  • Gunnam, Kiran||Wang, Weihuang||Choi, Gwan||Yeary, Mark

publication date

  • January 2007