Low-Power Embedded LDPC-H.264 Joint Decoding Architecture Based on Unequal Error Protection Conference Paper

abstract

• This paper presents a low-power embedded LDPCH. 264 decoding architecture to lower the baseband energy consumption of a channel decoder using joint source decoding and dynamic voltage and frequency scaling (DVFS). This method is developed for H.264 layered (data partitioned) video transmission over Low Density Parity Check (LDPC) codec. We exploit the fact that not all transmitted data require the same level of error protection; this is known as unequal error protection (UEP). In particular, we use variable iteration LDPC decoding along with H.264 data partitioning (DP). In this scheme, we determine and use the lowest values of iterations that are needed by the decoder to achieve pre-specified image qualities at the receiver, and apply DVFS to minimize power. 2010 IEEE.

name of conference

• 2010 5th International Conference on Future Information Technology

authors

• Choi, Gwan

published proceedings

• 2010 5th International Conference on Future Information Technology

author list (cited authors)

• Yang, Y. S., & Choi, G.

citation count

• 0

complete list of authors

• Yang, Yoon Seok||Choi, Gwan

publication date

• January 2010

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

Digital Object Identifier (DOI)

• 10.1109/futuretech.2010.5482744

International Standard Book Number (ISBN) 13

• 9781424469505

start page

• 1

end page

• 6

URL

• http://dx.doi.org/10.1109/futuretech.2010.5482744