Simulated fault injection: a methodology to evaluate fault tolerant microprocessor architectures Academic Article uri icon


  • This paper describes a simulation-based fault injection methodology to validate fault tolerant microprocessor architectures. The approach uses mixed-mode simulation (electrical/logic analysis), and injects transient errors in run-time, to assess the resulting fault-impact. To exemplify the methodology, a fault tolerant architecture which models the digital aspects of a dual channel, real-time jet engine controller is used. The level of effectiveness of the dual configuration to single and multiple transients is measured. The results indicate 100% coverage of single transients. Approximately 12 percent of the multiple transients affect both channels; none result in controller failure since two additional levels of redundancy exist. 1990 IEEE

published proceedings

  • IEEE Transactions on Reliability

author list (cited authors)

  • Choi, G. S., Iyer, R. K., & Carreno, V. A.

citation count

  • 26

complete list of authors

  • Choi, GS||Iyer, RK||Carreno, VA

publication date

  • January 1990