Fpga Based Implementation of Decoder for Array Low-Density Parity-Check Codes Conference Paper

abstract

• In the past few years, the Low Density Parity Check (LDPC) codes have received lot of attention for their excellent performance, and inherent parallelism involved in decoding them. In this work we consider a type of structured binary LDPC codes known as array LDPC codes, which have low encoding complexity and good performance, for implementation on Xilinx Field Programmable Gate Array (FPGA) device. 2005 IEEE.

name of conference

• Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.

authors

• Choi, Gwan

published proceedings

• Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.

author list (cited authors)

• Bhagawat, P., Uppal, M., & Choi, G.

citation count

• 10

complete list of authors

• Bhagawat, Pankaj||Uppal, Momin||Choi, Gwan

publication date

• January 2005

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings of the ... IEEE International Conference on Acoustics, Speech, and Signal Processing / sponsored by the Institute of Electrical and Electronics Engineers Signal Processing Society. ICASSP (Conference)  Journal

Digital Object Identifier (DOI)

• 10.1109/icassp.2005.1416232

International Standard Book Number (ISBN) 10

• 0780388747

International Standard Book Number (ISBN) 13

• 9780780388741

start page

• v-29-v-32

volume

• 5

URL

• http://dx.doi.org/10.1109/icassp.2005.1416232