Fpga Based Implementation of Decoder for Array Low-Density Parity-Check Codes
Additional Document Info
In the past few years, the Low Density Parity Check (LDPC) codes have received lot of attention for their excellent performance, and inherent parallelism involved in decoding them. In this work we consider a type of structured binary LDPC codes known as array LDPC codes, which have low encoding complexity and good performance, for implementation on Xilinx Field Programmable Gate Array (FPGA) device. 2005 IEEE.
name of conference
Proceedings. (ICASSP '05). IEEE International Conference on Acoustics, Speech, and Signal Processing, 2005.