Low-density parity-check decoder architecture for high throughput optical fiber channels Conference Paper

abstract

• A requirement-specific decoder design for forward error-correction in 2 Gbps optical fiber communication system is presented. Low-density parity-check codes are used to achieve high bit error rate performance. Several novel error- decoding architectures are proposed and their design configurations explored to identify optimal cost/performance design. Serial, parallel and scalable architectures are studied. The result is a scalable architecture that consists of 1.3 million CMOS gates running at 295 Mhz and it achieves a throughput of 2.51 Gbps.

name of conference

• Proceedings 21st International Conference on Computer Design

authors

• Choi, Gwan

published proceedings

• 21ST INTERNATIONAL CONFERENCE ON COMPUTER DESIGN, PROCEEDINGS

author list (cited authors)

• Selvarathinam, A., Kim, E., & Choi, G.

citation count

• 5

complete list of authors

• Selvarathinam, A||Kim, E||Choi, G

publication date

• January 2003

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Conference on Computer Design - VLSI in Computers and Processors  Journal

keywords

• Fibre Channel
• Hardware Scaling
• Ldpc Decoder
• Parallel Architecture
• Serial Architecture
• Vlsi

Digital Object Identifier (DOI)

• 10.1109/ICCD.2003.1240949

International Standard Book Number (ISBN) 10

• 0-7695-2025-1

start page

• 520

end page

• 525

URL

• http://dx.doi.org/10.1109/iccd.2003.1240949