Accelerated Dual-Path Asynchronous Circuit
- Additional Document Info
- View All
2004-2012 IEEE. This brief presents a novel design approach that accelerates an asynchronous circuit system by circumventing transient-fault-induced delays and tolerates latchups and other permanent faults. Specifically, a dual-path asynchronous circuit design and an associated arbiter are developed. Asynchronous circuits inherently tolerate transient errors by incurring an additional delay. This, in turn, can debilitate the circuit to suspend in an environment where the fault rate (FR) is excessively high. The dual-path design approach presented in this brief eliminates this problem by using whichever output or outcome combination becomes valid first from the two asynchronous stages. The design approach is illustrated with a low-density parity-check decoder architecture that must exhibit a high degree of reliability in error-prone operating conditions. Results show that the decoder reduces the delay overhead from 19.5% to 7.5% when the FR is 400/clock cycle. However, the arbiter only introduces about 2% area overhead in addition to the duplication overhead, which is exactly 2X.
IEEE Transactions on Circuits & Systems II Express Briefs
author list (cited authors)
Che, T., Xu, J., & Choi, G.
complete list of authors
Che, Tiben||Xu, Jingwei||Choi, Gwan